For a particular inverter design using a power supply VDD,
Chapter 13, Problem 13.3(choose chapter or problem)
For a particular inverter design using a power supply VDD, VOL = 0.1VDD, VOH = 0.8VDD, VIL = 0.4VDD, and VIH = 0.6VDD. What are the noise margins? What is the width of the transition region? For a minimum noise margin of 1 V, what value of VDD is required?
Unfortunately, we don't have that question answered yet. But you can get it answered in just 5 hours by Logging in or Becoming a subscriber.
Becoming a subscriber
Or look for another answer