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Show that (a) sinh(:: +:ri) = -sinh:::(/>) cosh(:: +;ri) -

Complex Variables and Applications | 9th Edition | ISBN: 9780073383170 | Authors: James Ward Brown ISBN: 9780073383170 169

Solution for problem 3.68 Chapter Chapter 3

Complex Variables and Applications | 9th Edition

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Complex Variables and Applications | 9th Edition | ISBN: 9780073383170 | Authors: James Ward Brown

Complex Variables and Applications | 9th Edition

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Problem 3.68

Show that (a) sinh(:: +:ri) = -sinh:::(/>) cosh(:: +;ri) - cosh::: (c) tanh

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Embedded system-a system controlled by one or more EPROM PROGRAMMING computers/microprocessors that are internal to the system. [flowchart]-how many times does the programmer try to Microcontroller- “computer on a chip” program a difficult cell before It quits 10 A realtime system must insure that a task is completed How does the programmer program the EPROM Programs all within a certain time span. Ex: air traffic control system, the cells then checks each one for validity current location [timing diagram] When designing an embedded system: real time execution of How long must programmer wait to insure the DATA is valid tasks, physical size and environment, pwr consumption, User after the EPROM is told to output the cell data written to it Interface, cost v func, mem needs, hardware vs software. tDV Who makes the processors discussed in class: freescale or What point in time does the EPROM programmer read the motorola data to be verified from the bus The second rising edge of HC12 processor CE# two 8bit accumulators A and B which can be ganged together, How long must the DATA be stable before the EPROM latches 128kb flash on board, 2 16bit regs X&Y, 8MHz bus clock,16bit the data into memory tDS machine. 16bit stack pointer,16 bit prog counter,hc9512 has max 25mhz clock and 512kb flash How long must the address by stable before the EPROM 9s12 pinout: latches the data into memory tAS 3 spi ports, ext addess lines at A,B,K, background debugger What signal tells the EPROM to output the cell data which was @pin 23, enhanced capture timer @ port t,sci @ port 5, 4kb of written to it CE EEPROM, CAN ports @ j&M address at most 64kb of ext. Ram What point in time does the EPROM read the data it is to without expanded port K, 1 pc port, ext data lines are ports program into its cell The first rising edge of CE# A&B What signal determines whether input or output data is on the Energy Calculations bus OE or OE# or OE#Vpp or OE/Vpp (years) Current draw(A)=(Amp-Hrs)/(Yrs*365*24) How does the programmer program the EPROM Programs all (2-modes) Average(mA)= P5C(mA)*X-Run(mA)*(1-x) cells then checks each one for validity (3modes) Average(mA)=run(mA)*(1-x-y) [Timing diagram] +wait(mA)*Y+STOP(mA)*(1-x-y) How long must programmer wait to insure the DATA is valid Average(amps)=(Bat*amp-hours)/hrs after the EPROM is told to output the cell data written to it Chip Addressing tDV Ex: first address of a 4k mem chip is 324k with 20 bit What point in time does the EPROM programmer read the addresses data to be verified from the bus The second rising edge of A (4k*1024) =2^addresslines CE# B for a 20 bit address, set all address lines to X starting at bit How long must the DATA be stable before the EPROM latches 0. (0000 0000 xxxx xxxxx xxxx) Finally, set the starting the data into memory 1D address for the chip starting at bit 19 (0101 0001 xxxx xxxx How long must the address by stable before the EPROM xxxx) latches the data into memory 1AS Address Decoding What signal tells the EPROM to output the cell data which was No gaps- all 1’s are critical, a 0 is critical if changing it to a 1 written to it CE will make it identical to another address. If a 0 is critical all the What point in time does the EPROM read the data it is to ones to the right are too. If a 0 is non critical all the ones program into its cell The first rising edge of CE# under are too. An x can be a 0 or a 1 when checking for What signal determines whether input data or ooutput data is critical 0’s. on the data bus OE or OE# or OE#Vpp or OE/Vpp Gaps- to fix a gap, all chip sizes must be a multiple of the What point in time does the EPROM read the data it is to starting address. If not, increase the starting address until it’s program into its cell The first rising edge of CE# at least a multiple of 1*(start addr.). All 1’s are critical, 0’s are DEVELOPMENT TOOLS a case by case basis. Reset switch,com ports, lcd display, 7 segment display, LEDS, Decoder keypad switches, amplifiers/op amps, optoisolators, relays, If ANY chip select input (CS1, CS2,CS3) is not active, no SCRs/triacs, buzzers, potentiometers, DACs, dip switches, outputs thermometers, breadboards, expansion ports/slots/connectors If ALL chip select inputs (cs1,cs2,cs3) are active, address A2 Whats the name of an electronmechanical device that is used A1 A0=Y# is output to switch higher voltage and/or higher current devices Relay Decoder gate or scr or triac 1 determine what your inputs must be to activate the chip DPDT-double pole double throw, SPDT-single pole single throw select line. If the chip select requires a low, then the chip Circuitry that is used to interface two different chips together must output a 0. If high, then a 1. 2 write out A19-A12. For called Glue logic lines not required by the chip, put an x. 3. Convert both sets What kind of IC is used to isolate a low voltage microprocessor of 4 bits to hex. Answers 0x[9 or b][c or d or f][x][x][x] are circuit from a higher voltage motor Optoisiolator valid Name for a program which takes c code and creates code for 19 18 17 16 15 14 13 12 a microcontroller Cross compiler 1 0 x 1 1 1 x x Software/hardware which allows you to start/stop execution [9B ] [C,D,F ] while it is executing Debugger Memory general |s|1|11|0038|8656c6c6f20776f726c642e0a0042|42 SRAM is typically used in level 1&2 cache and NVRAM| S-start code,1-record type,11-byte count,0038-address,[42]- variables are stored in RAM, Volatile, SRAM, and DRAM| data,42-checksum Advantages of DRAM: lower power use (at use), higher Addressing density, less expensive| Advantages of SRAM: lower power Take port b and convert to binary and the rightmost bit is the use at rest, simpler to implement, faster, can be on same die value of ADDR[]. If ECLK is 0 it is preparing, if it is a 1 it is as processor logic|sram is made of transistors| dram is made doing the action out of small capacitors | voltatile memory: sram, dram, Ch5 general srdram| nonvolatile memory: EEPROM, EPROM, nvram, otp What signal from the 9s12 is used in conjunction with the rom, flash, masked rom, prom| stack in a embedded system is r/w# line to determine whether or not 8 or 16 bit data is being store in: RAM, volatile, SRAM, DRAM (any one of)| system read LSTRB states in an embed. Sys, is stored in: rom, non volatile, prom, The term ‘glue logic’ refers to the added circuitry necessary EPROM, or EEPROM |program instructions an embedded to interface 2 or more chips together system:rom, non-volatile, prom, EPROM, EEPROM | user The 256 in the part number MC9S12DP256B refers to the settings in an embedded system: either rom, non volatile, amount of memory in the chip prom, EPROM, EEPROM Flash memory is used to hold instructions on the chip Which of the following is/are not found on the MC9S12 Piezo Take bits given as 1’s and the rest 0’s. take the inverse of the Electric Buzzer, Digital to Analog Converter, bits, convert to hex, and AND (&) with PTH. (PTH & ~0x01) Temperature Sensor Bitmasking while What is a compiler called which generates code for a process Determine what port h bits are being checked, determine other than the one it is running on Cross Compiler when these are tripped in order to exit the loop. 0 equals What signal from the MC9S12 is used to determine whether or false, and all other values are true if no test occurs. While (pth not a memory chip is being read from or written to RW or & 0x03) ==0); PTJ=O; Porth[0] and[1] are zero R/W or R/W# Bitmasking XOR What type of memory is located at the very beginning (lowest Convert the hex to binary, follow the required operations addresses) of the MC9S12Memory Map by default Registers within the code. Note: XOR operator (^) produces a 1 if the or control registers two input bits differ or 0 if same. Find the output and convert What signal is shown at the top of this timing diagram back to hex. (indicated with )ELCK BItmasking XOR code In the glue logic below the signal A is [ECLK] and the signal B Denote in the answer the genetic changes from the OldSw to is [R/W#] the NewSw and how that coordinates with the output ChangeSw, Make sure there’s a 1 compared to a 1, 0 to a 0, 1 to a 0, and 0 to a 1 in the bits of Oldsw and newsw to find the relationship of them and ChangedSw. Key Pad If a for loop containing key and I, the first valid keycode pressed will be the first inputted and outputted value. If two keys (and only two keys) are pressed on the same row, their hex value won’t match any value and the output will be 0 In the glue logic below the signal A is [WE#] and the signal B (NOT ‘0’). is [OE#] Ex if 5,9,c and F are pressed, then 5 will be the output. If c and f are pressed, then the output will be 0,(not ‘0’). If the for loop contains row, then the answer for the output of this code will be in a 4 digit hex form. Take each row as a 4 digit binary code and align them like so: row 3|row 2|row 1| row 0|. Each key that is pressed on each row is denoted as a 1 MEMORY INTERFACING in binary. Multiple keys can be pressed so multiple ones can Chip 0 is a 2^[c] kb chip (D=A_) Chip is low order if D0(F) and D07(G) are D8 and d15 appear in a row. Convert the 16 digit long binary number into Chip 0 starting address is A and B set high w/ everything else hex. That’s your answer. a 0 (ie 0x60000) Example: if 1,4,6,9 and D are pressed, the out put will be 0x2522. Chip 0 ending address is a and b high with everything before Pull Ups D(A_) set to 1 (0x67FFFF) Big endian if lstrb goes into low order chip and A0 will go to If PortH is connected to 5v, then it’s a 1. If it’s to ground, then high order chip it’s a 1. Be careful of the placement of the resistor and the C and H are always A1 delay state of the circuit. Reset Mode Fan Out The formulas are Fanout(h)=I(OH)/I(IH) and ROMON set to 1 makes internal flash usable Fanout(I)=I(OL)/I(IL) ROMONCTL set to 1 allows for ROMON bit in the MISC register to be set Next use IOH(driver)/IOH(driven) and IOL(driver)/IIL(driven. GENERAL CHAP 6 Take the minimum value of these and round down to the Latched used in class is 374 nearest whole number Isolated i/o: pros: simultaneous memory and i/o Cons: SPP timing NOP =((# of STRB lows)*(frequency*n)/clockticks) -1, where n additional pins needed for address, data control, additional is in seconds, frequency is in Hz. Round your final answer up if isntructions needed to access i/o Memory mapped i/o: pros- no addition pins or instructions it’s not an integer. necessary cons- less memory can be addressed More Reset Mode PAL DECODING MSB of the address and data are located on Port[A] and the Convert starting and ending address to binary. where the two LSB of the address and data are located on Port B in expanded wide mode values differ put an x MSB of the address is located on port[a] and the lsb of the 10000001010 (first ten bits of output) 10000001000 (first ten bits of input) address is located on port[b] and the data is located on 100000010xx(answer) port[a] in expanded narrow mode PIM(PORT INTEGRATION MODULE) 8 bit external memory bus with emulation MODA =1, data direction reg(ddrn), i/o register(ptn), input register(PTIn), MODB=0,MODC=0 16bit external mem bus in regular mode reduced drive register (RDRn),pull enable register(PERn), MODA=1,MODB=1,MODC=1 polarity select register(PPSn), port interrupt register(PIEPn), port interrupt flag register (PIFn), port wired-or mode register 16bit external mem bus in emulation mode (WOMn) MODA=1,MODB=1,MODC=0 PIM INITIALIZATION Not use expanded memory MODA=0,MODB=0,MODC=X More Chap 6 General DDR(p) Data Direction Port p, 1 output, 0 input Pull-down resistor- pulls an input down to zero by latching it to PER(p) Port Pull Device Enable, 1 enable if input, 0 disable if ground input PIE(p) Port Interrupt Enable, 1 enable/unmask, 0 Volatile unsigned char- volatile allows the variable to be disable/mask changed externally PPS(p) Port Polarity Select, 1Enable Pull Down+rising edge,0- Linear select addressing of i/o- pros: simple selection logic, 1 port per ad.Line Enable Pull Up+rising edge Con- wasteful addressing RDRH Port Reduced Drive Register, 1 bits given, 0 elsewhere A latch is needed to store the address from the 9s12 when Bitmasking OR(set) Take bits given as 1’s and the rest or 0’s. OR the equivalent communicating with an i/o device because the bus is with PTH (ie PTH | 0x01) multiplexed so the address must be stored while data is put Bitmasking AND(clear) on the bus The latch’s G input is not-ed so it has to connect to 5v to make it a zero. 74373 uses an enable while the 74374 latches values on the This register can determine whether an interrupt is detected rising edge of a clock on either the rising edge or falling edge of a signal. PPSn Everything is done in parallel because there are plenty of jobs Which register is written to in order to chang the values of a the computer has to do and all of them are performed ports pinsPTn individually. Therefore, parallelism makes everything WAY What port only has 4 pins instead of 8 J faster and other programs does not have for another to Which register needs to be configured before ever outputting complete before it executes. a value to a certain port pin DDRn What is a typical size/value of a pullup resistor 4.7 KOhm — This register determines whether or not a transition on a port 10 KOhm pin will produce an interrupt. PIEn More PIM The ISA level directly supports serial instructions. False an open drain output allows for ‘wired ORing’ or pins. True Which register ddetermines if port pins will be used as input this register can be used to detect overloads or shorts at pins. or outputDDRn PTIn Which register determines if port pins will act as an OR gate this register can be used to internally connect a resistor from when its pins are tied together or not WOMn a port pin to either Vcc or Vdd if the corresponding pin is set This register reads the state of the register buffer if reading a to input. PERn pin is set to output. PTn In order to know which pin an interrupt has occurred on this register must be read. PIFn A pull up resistor is generally used to make an input pin’s Believe in yourself! Everyone knows you’re going to do default value 1. great, no matter where you go or what you do, as long This register can determine whether the pull resistor is pull up as you try your best and be nice to everyone. We’re all or down.PPSn dead in 90 years, so enjoy everything to the fullest.

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Textbook: Complex Variables and Applications
Edition: 9
Author: James Ward Brown
ISBN: 9780073383170

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Show that (a) sinh(:: +:ri) = -sinh:::(/>) cosh(:: +;ri) -