The following circuit is intended to be a gated latch
Chapter 11, Problem 11.15(choose chapter or problem)
The following circuit is intended to be a gated latch circuit where the signal G is the gate.
(a) Derive the next-state equation for this circuit using Q as the state variable and P as an output.
(b) Construct the state table and output table for the circuit. Circle the stable states of the circuit.
(c) Are there any restrictions on the allowable input combinations on M and N? Explain your answer.
(d) Is the output P usable as the complement of Q? Verify your answer.
(e) Assume that Gate 1 has a propagation delay of 30 ns and Gates 2, 3, and 4 have propagation delays of 10 ns. Construct a timing diagram for the circuit for the following input change: M = N = Q = 0 with G changing from 1 to 0.
Unfortunately, we don't have that question answered yet. But you can get it answered in just 5 hours by Logging in or Becoming a subscriber.
Becoming a subscriber
Or look for another answer