Design a counter which counts in the sequence that has been assigned to you. Use D flip-flops and NAND gates. Simulate your design using SimUaid. (a) 000, 001, 011, 101, 111, 010, (repeat) 000, . . . (b) 000, 011, 101, 111, 010, 110, (repeat) 000, . . . (c) 000, 110, 111, 100, 101, 001, (repeat) 000, . . . (d) 000, 100, 001, 110, 101, 111, (repeat) 000, . . . (e) 000, 010, 111, 101, 011, 110, (repeat) 000, . . . Present State Next State Q Q+ M N 0 0 0 1 1 0 1 1 404 Unit 12 (f ) 000, 100, 001, 111, 110, 101, (repeat) 000, . . . (g) 000, 010, 111, 101, 001, 110, (repeat) 000, . . . (h) 000, 101, 010, 011, 001, 110, (repeat) 000, . . . (i) 000, 100, 010, 001, 110, 111, (repeat) 000, . . . (j) 000, 001, 111, 010, 110, 011, (repeat) 000, . . . (k) 000, 100, 010, 001, 101, 111, (repeat) 000, . . . (l) 000, 011, 111, 110, 001, 100, (repeat) 000, . . . (m) 000, 100, 111, 110, 010, 011, (repeat) 000, . . . (n) 000, 011, 111, 110, 010, 100, (repeat) 000, . . .
12.10 Design a counter which counts in the sequence that has been assigned to you. Use D flip-flops and NAND gates. Simulate your design using SimUaid.
(a) 000, 001, 011, 101, 111, 010, (repeat) 000,...
(b) 000, 011, 101, 111, 010, 110, (repeat) 000,...
(c) 000, 110, 111, 100, 101, 001, (repeat) 000,...
(d) 000, 100, 001, 110, 101, 111, (repeat) 000,...
(e) 000, 010, 111, 101, 011, 110, (repeat) 000,...
(f ) 000, 100, 001, 111, 110, 101, (repeat) 000,...
(g) 000, 010, 111, 101, 001, 110, (repeat) 000,...
(h) 000, 101, 010, 011, 001, 110, (repeat) 000,...
(i) 000, 100, 010, 001, 110, 111, (repeat) 000,..
(j) 000, 001, 111, 010, 110, 011, (repeat) 000,...
(l) 000, 011, 111, 110, 001, 100, (repeat) 000,...
(m) 000, 100, 111, 110, 010, 011, (repeat) 000,...
(n) 000, 011, 111, 110, 010, 100, (repeat) 000,...
Step By Step Solution
Step 1 of 15
To design a counter, first let's have a look at the transition diagram showing the counter sequence. Then write the excitation table of the required flip flop and derive the flip flop input equations using k-map. After that convert these equations into NAND form using double negation and De-Morgan’s Theorem.