A modulo 8 counter cycles through the states Q0Q1Q2Q3 =

Chapter 17, Problem 17.18

(choose chapter or problem)

A modulo 8 counter cycles through the states \(Q_{0} Q_{1} Q_{2} Q_{3} = 1000, 1100, 0100, 0110, 0010, 0011, 0001, 1001\). The counter has eight outputs: \(Z_{0} = 1\) when the counter is in state 1000 and the CLK is 0 and \(Z_{0} = 0\) otherwise; \(Z_{1} = 1\) when the counter is in state 1100 and the CLK is 0 and \(Z_{1} = 0\) otherwise, . . .; \(Z_{7} = 1\) when the counter is in state 1001 and the CLK is 0 and \(Z_{7} = 0\) otherwise. The counter has an asynchronous, active-low reset input ClrN.

(a) Derive minimum equations for the counter outputs.

(b) Assume the counter is implemented using D flip-flops. Find minimum input equations for the flip-flops.

(c) Assume the counter is implemented using D-CE flip-flops. Find minimum input equations for the flip-flops.

(d) Write a VHDL behavioral description of the counter. Assume the flip-flops are positive edge triggered.

(e) Write a VHDL dataflow description of the counter using the equations from part (b). Simulate the counter for a cycle to verify your code.

(f ) Write a VHDL dataflow description of the counter using the equations from part (c). Simulate the counter for a cycle to verify your code.