The following iterative circuit is a priority selection
Chapter 17, Problem 17.21(choose chapter or problem)
The following iterative circuit is a priority selection circuit. When one or more of the inputs is 1, osel = 0 and \(y_{i} = 1\) where i is the largest index such that \(x_{i} = 1\). If none of the inputs is 1, then all outputs are 0 and osel = 1. The four modules in the circuit are identical.
(a) Derive the logic equations that describe the Pr module.
(b) Using your equations from part (a), write VHDL code that gives a dataflow description of the Pr module.
(c) Using the VHDL module defined in part (b), write structural VHDL code that specifies the 4-bit priority selector.
(d) Use the Direct VHDL simulator to obtain the signal values for the three input combinations: x = 1000, x = 0111, and x = 0000. Record the waveform report from the simulator.
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