Give the state table implemented by the following VHDL
Chapter 17, Problem 17.27(choose chapter or problem)
Give the state table implemented by the following VHDL code.
entity Problem17_27 is
port(X1, X2, CLK: in bit;
Z: out bit);
end Problem17_27;
architecture Table of Problem17_27 is
signal State, Nextstate: integer range 0 to 2 : = 0;
signal X12: bit_vector(0 to 1);
begin
X12 <= X1&X2;
process(State, X12) --Combinational Circuit
begin
case State is
when 0 => Z <= '0';
case X12 is
when "00" => Nextstate <= 0;
when "01" => Nextstate <= 1;
when "10" => Nextstate <= 2;
when "11" => Nextstate <= 0;
end case;
when 1 => Z <= '0';
case X12 is
when "00" => Nextstate <= 0;
when "01" => Nextstate <= 1;
when "10" => Nextstate <= 2;
when "11" => Nextstate <= 1;
endcase;
when 2 => Z <= '1';
caseX12is
when "00" => Nextstate <= 0;
when "01" => Nextstate <= 1;
when "10" => Nextstate <= 2;
when "11" => Nextstate <= 2;
end case;
end case;
end process;
-- the clocked process goes here, same as in Problem 17.25.
end Table;
Unfortunately, we don't have that question answered yet. But you can get it answered in just 5 hours by Logging in or Becoming a subscriber.
Becoming a subscriber
Or look for another answer