The binary multiplier of Figure 18-7 has been redesigned
Chapter 18, Problem 18.5(choose chapter or problem)
The binary multiplier of Figure 18-7 has been redesigned so that whenever addition occurs the multiplier bit (M) will be set to 0. Specifically, the Ad signal is now connected to a synchronous clear input on only the rightmost flip-flop of the product register of Figure 18-7. Thus, if M is 1 at a given clock time and addition takes place, M will be 0 at the next clock time. Now, we can always add when M = 1 and always shift when M = 0. This means that the control circuit does not have to change state when M = 1, and the number of states can be reduced from ten to six. Draw the resulting state graph for the multiplier control with six states.
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