An NMOS transistor is connected in the bias circuit of Fig. 7.48(c), with VG = 5 V and
Chapter 7, Problem 7.95(choose chapter or problem)
An NMOS transistor is connected in the bias circuit of Fig. 7.48(c), with VG = 5 V and RS = 3 k. The transistor has Vt = 1 V and kn = 2 mA/V2 . What bias current results? If a transistor for which kn is 50% higher is used, what is the resulting percentage increase in ID?
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