Figure P7.103 shows a variation of the feedback-bias circuit of Fig. 7.50. Using a 5-V
Chapter 7, Problem 7.103(choose chapter or problem)
Figure P7.103 shows a variation of the feedback-bias circuit of Fig. 7.50. Using a 5-V supply with an NMOS transistor for which Vt = 0.8 V, kn = 8 mA/V2 , and = 0, provide a design that biases the transistor at ID = 1 mA, with VDS large enough to allow saturation operation for a 2-V negative signal swing at the drain. Use 22 M as the largest resistor in the feedback-bias network. What values of RD, RG1, and RG2 have you chosen? Specify all resistors to two significant digits. RD VDD RG1 RG2 Figure P7.103
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