The system is to be controlled with a digital controller having a sampling period of T =
Chapter 8, Problem 8.14(choose chapter or problem)
The system is to be controlled with a digital controller having a sampling period of T = 0.1 sec. Using a z-plane root locus, design compensation that will respond to a step with a rise time tr 1 sec and an overshoot Mp 5%. What can be done to reduce the steady-state error?
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