The circuit shown in Figure P 8.3-1 is at steady state before the switch closes at time

Chapter 8, Problem P8.3-1

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QUESTION:

The circuit shown in Figure P 8.3-1 is at steady state before the switch closes at time t = 0. The input to the circuit is the voltage of the voltage source, 12 V. The output of this circuit is the voltage across the capacitor, v(t). Determine v(t) for t > 0.

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QUESTION:

The circuit shown in Figure P 8.3-1 is at steady state before the switch closes at time t = 0. The input to the circuit is the voltage of the voltage source, 12 V. The output of this circuit is the voltage across the capacitor, v(t). Determine v(t) for t > 0.

ANSWER:

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