- 11.11.1: Assume that the inverter in the given circuit has a propagation del...
- 11.11.2: A latch can be constructed from an OR gate, an AND gate, and an inv...
- 11.11.3: This problem illustrates the improper operation that can occur if b...
- 11.11.4: Design a gated D latch using only NAND gates and one inverter.
- 11.11.5: What change must be made to Figure 11-19(a) to implement a falling-...
- 11.11.6: A reset-dominant flip-flop behaves like an S-R flip-flop, except th...
- 11.11.7: Complete the following timing diagram for the flip-flop of Figure 1...
- 11.11.8: Complete the following diagrams for the falling-edge-triggered D-CE...
- 11.11.9: (a) Complete the following timing diagram for a J-K flip-flop with ...
- 11.11.10: Convert by adding external gates: (a) a D flip-flop to a J-K flip-f...
- 11.11.11: Complete the following timing diagram for an S-R latch. Assume Q be...
- 11.11.12: Using a truth table similar to Figure 11-8(b), confirm that each of...
- 11.11.13: An AB latch operates as follows: If A = 0 and B = 0, the latch stat...
- 11.11.14: (a) Construct a state table for this circuit and identify the stabl...
- 11.11.15: The following circuit is intended to be a gated latch circuit where...
- 11.11.16: Analyze the latch circuit shown. (a) Derive the next-state equation...
- 11.11.17: Derive the characteristic equations for the following latches and f...
- 11.11.18: Complete the following timing diagrams for a gated D latch. Assume ...
- 11.11.19: Complete the following diagrams for the rising-edge-triggered D fli...
- 11.11.20: A set-dominant flip-flop is similar to the reset-dominant flip-flop...
- 11.11.21: Fill in the timing diagram for a falling-edge-triggered S-R flip-fl...
- 11.11.22: Fill in the timing diagram for a falling-edge-triggered J-K flip-fl...
- 11.11.23: (a) Find the input for a rising-edge-triggered D flip-flop that wou...
- 11.11.24: Here is the diagram of a 3-bit ripple counter. Assume Q0 = Q1 = Q2 ...
- 11.11.25: Fill in the following timing diagram for a rising-edge-triggered T ...
- 11.11.26: The ClrN and PreN inputs introduced in Section 11.8 are called asyn...
- 11.11.27: (a) Construct a D flip-flop using an inverter and an S-R flip-flop....
- 11.11.28: Redesign the debouncing circuit of Figure 11-9 using the S-R latch ...
- 11.11.29: (a) Use the characteristic equation for the gated D latch to implem...
- 11.11.30: Consider converting the gated S-R latch of Figure 11-11 into a gate...
- 11.11.31: (a) Derive a NOR-gate version of the gated S-R latch analogous to F...
- 11.11.32: (a) Redesign the circuit of Figure 11-32 so that P+ and Q+ are free...
- 11.11.33: For each of the 8 stable states of Figure 11-33, consider changing ...
- 11.11.34: Label the states in Figure 11-34 from a = 000 to h = 100. Determine...

# Solutions for Chapter 11: Latches and Flip-Flops

## Full solutions for Fundamentals of Logic Design | 7th Edition

ISBN: 9781133628477

Solutions for Chapter 11: Latches and Flip-Flops

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