- 14.14.1: Design the inverter in Fig. 14.12(a) to provide VOL = 90 mV and to ...
- 14.14.2: For the current-steering circuit in Fig. 14.19, let VCC = 5 V, IEE ...
- 14.14.3: In an attempt to reduce the required value of RD to 10 k, the desig...
- 14.14.4: In an attempt to reduce the required value of RD to 10 k, the desig...
- 14.14.5: It is required to find VM for the pseudo-NMOS inverter of Fig. 14.2...
- 14.14.6: Consider a CMOS inverter fabricated in a 0.13-m process for which V...
- 14.14.7: A CMOS inverter utilizes VDD = 5 V, Vtn = Vtp = 1 V, and nCox = 2pC...
- 14.14.8: A capacitor C whose initial voltage is 0 is charged to a voltage VD...
- 14.14.9: For the inverter of Fig. 14.18(a), let the on-resistance of PU be 2...
- 14.14.11: For a CMOS inverter fabricated in a 0.18-m process with VDD = 1.8 V...
- 14.14.12: For a CMOS inverter fabricated in a 0.13-m process, use the equival...
- 14.14.13: Consider the inverter specified in Example 14.7 when loaded with an...
- 14.14.14: In an attempt to decrease the area of the inverter in Example 14.7,...
- 14.14.15: For the inverter of Example 14.7, find the theoretical maximum freq...
- 14.14.16: For the inverter analyzed in Example 14.7: (a) Find the intrinsic a...
- 14.14.17: For a process technology with L = 0.18 m, n = 1.5, p = 3, give the ...
- 14.14.18: For the scaled NAND gate in Exercise 14.17, find the ratio of the m...
- 14.14.19: Find the dynamic power dissipation of the inverter analyzed in Exam...
- 14.14.21: A particular inverter circuit initially designed in a 0.5-m process...
- 14.14.22: For the CMOS inverter analyzed in Example 14.7, it was found that C...
- 14.14.23: A logic-circuit type intended for use in a digital-signal-processin...
- 14.14.24: Design the inverter circuit in Fig. 14.12(a) to provide VOH = 1.2 V...
- 14.14.25: For the current-steering circuit in Fig. 14.19, VCC = 2 V, IEE = 0....
- 14.14.26: Refer to the analysis of the resistive-load MOS inverter in Example...
- 14.14.27: Refer to the analysis of the resistive-load MOS inverter in Example...
- 14.14.28: An earlier form of logic circuits, now obsolete, utilized NMOS tran...
- 14.14.29: For the pseudo-NMOS inverter analyzed in Example 14.3 and in Exerci...
- 14.14.31: Consider a CMOS inverter fabricated in a 65-nm CMOS process for whi...
- 14.14.32: Consider a CMOS inverter fabricated in a 0.25-m CMOS process for wh...
- 14.14.33: For a technology in which Vtn = 0.3VDD, show that the maximum curre...
- 14.14.34: A CMOS inverter for which kn = 5kp = 200 A/V2 and Vt = 0.5 V is con...
- 14.14.35: There are situations in which QN and QP of the CMOS inverter are de...
- 14.14.36: Consider the CMOS inverter of Fig. 14.22 withQN and QP matched and ...
- 14.14.37: Repeat Example 14.4 for a CMOS inverter fabricated in a 0.13-m proc...
- 14.14.38: For the circuit shown in Fig. P14.38, let switch S open at t = 0. (...
- 14.14.39: For the circuit in Fig. P14.39, let C be charged to 10 V and switch...
- 14.14.41: For the inverter of Fig. 14.18(a) with a capacitance C connected be...
- 14.14.42: A logic inverter is implemented using the arrangement of Fig. 14.18...
- 14.14.43: In a particular logic family, the standard inverter, when loaded by...
- 14.14.44: Consider an inverter for which tPLH , tPHL, tTLH , and tTHL are 20 ...
- 14.14.45: For a CMOS inverter fabricated in a 0.13-m process with VDD = 1.2V,...
- 14.14.46: Consider a matched CMOS inverter fabricated in the 0.13-m process s...
- 14.14.47: For the CMOS inverter in Exercise 14.11 use the method of equivalen...
- 14.14.48: Use the method of equivalent resistance to determine the propagatio...
- 14.14.49: Use the method of equivalent resistance to design an inverter to be...
- 14.14.51: Use the method of average currents to estimate tPHL, tPLH , and tP ...
- 14.14.52: Find the propagation delay for a minimum-size inverter for which k ...
- 14.14.53: A matched CMOS inverter fabricated in a process for whichCox = 3.7 ...
- 14.14.54: An inverter whose equivalent load capacitance C is composed of 15 f...
- 14.14.55: In this problem we investigate the effect of the selection of the r...
- 14.14.56: Consider the CMOS gate shown in Fig. 14.9. Specify W/L ratios for a...
- 14.14.57: Find appropriate sizes for the transistors used in the exclusive-OR...
- 14.14.58: Consider a four-input CMOS NAND gate for which the transient respon...
- 14.14.59: Figure P14.59 shows two approaches to realizing the OR function of ...
- 14.14.61: A chain of four inverters whose sizes are scaled by a factor x is u...
- 14.14.62: The purpose of this problem is to find the values of n and x that r...
- 14.14.63: An IC inverter fabricated in a 0.18-m CMOS process is found to have...
- 14.14.64: Consider a logic inverter of the type shown in Fig. 14.18. Let VDD ...
- 14.14.65: In a particular logic-circuit technology, operating with a 3.3-V su...
- 14.14.66: A collection of logic gates for which the static power dissipation ...
- 14.14.67: A particular logic gate has tPLH and tPHL of 30 ns and 50 ns, respe...
- 14.14.68: We wish to investigate the design of the inverter shown in Fig. 14....
- 14.14.69: A logic-circuit family with zero static power dissipation normally ...

# Solutions for Chapter 14: CMOS Digital Logic Circuits

## Full solutions for Microelectronic Circuits (The Oxford Series in Electrical and Computer Engineering) | 7th Edition

ISBN: 9780199339136

Solutions for Chapter 14: CMOS Digital Logic Circuits

Get Full SolutionsChapter 14: CMOS Digital Logic Circuits includes 63 full step-by-step solutions. This expansive textbook survival guide covers the following chapters and their solutions. This textbook survival guide was created for the textbook: Microelectronic Circuits (The Oxford Series in Electrical and Computer Engineering) , edition: 7. Microelectronic Circuits (The Oxford Series in Electrical and Computer Engineering) was written by and is associated to the ISBN: 9780199339136. Since 63 problems in chapter 14: CMOS Digital Logic Circuits have been answered, more than 27968 students have viewed full step-by-step solutions from this chapter.