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Assuming a base CPI of 1.0 without any memory stalls, what
Chapter 5, Problem 5.6.3(choose chapter or problem)
Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?
For the next three problems, we will consider the addition of an L2 cache to P1 to presumably make up for its limited L1 cache capacity. Use the L1 cache capacities and hit times from the previous table when solving these problems. The L2 miss rate indicated is its local miss rate.
\(\begin{array}{|c|c|c|}
\hline \text { L2 Size } & \text { L2 Miss Rate } & \text { L2 Hit Time } \\
\hline \text { 1 MiB } & 95 \% & 5.62 \mathrm{~ns} \\
\hline
\end{array}\)
Questions & Answers
QUESTION:
Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?
For the next three problems, we will consider the addition of an L2 cache to P1 to presumably make up for its limited L1 cache capacity. Use the L1 cache capacities and hit times from the previous table when solving these problems. The L2 miss rate indicated is its local miss rate.
\(\begin{array}{|c|c|c|}
\hline \text { L2 Size } & \text { L2 Miss Rate } & \text { L2 Hit Time } \\
\hline \text { 1 MiB } & 95 \% & 5.62 \mathrm{~ns} \\
\hline
\end{array}\)
Step 1 of 2
Given, main memory access takes 70ns and that memory accesses are 36% of all instruction.
\(\text { Total } C P I=\text { base } C P I+\text { load } \times\left(\frac{\text { memory accesses }}{L 1 \text { hit time }}\right) \times L 1 \text { miss rate }\)