The linear model of a phase detector (phase-lock loop) can be represented by Figure P6.7

Chapter 0, Problem P6.7

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The linear model of a phase detector (phase-lock loop) can be represented by Figure P6.7 [9].The phaselock systems are designed to maintain zero difference in phase between the input carrier signal and a local voltage-controlled oscillator. Phase-lock loops find application in color television, missile tracking, and space telemetry. The filter for a particular application is chosen as F(s) = 10(5 + 10) (s + 1)(5 + 100)' We want to minimize the steady-state error of the system for a ramp change in the phase information signal, (a) Determine the limiting value of the gain KaK = Kv in order to maintain a stable system, (b) A steady-state error equal to 1 is acceptable for a ramp signal of 100 rad/s. For that value of gain Kv, determine the location of the roots of the system.