For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, and i are given and could be considered 32-bit integers as declared in a C program. Use a minimal number of MIPS assembly instructions. f = g + ( h ? 5 ) ;
Read moreTextbook Solutions for Computer Organization and Design
Chapter 2 Problem 2.16
Question
Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields:
op=0, rs=3, rt=2, rd=3, shamt=0, funct=34
Solution
The first step in solving 2 problem number 27 trying to solve the problem we have to refer to the textbook question: Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields: op=0, rs=3, rt=2, rd=3, shamt=0, funct=34
From the textbook chapter Instructions: Language of the Computer you will find a few key concepts needed to solve this.
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Title
Computer Organization and Design 5
Author
David A. Patterson
ISBN
9780124077263
Provide the type, assembly language instruction, and
Chapter 2 textbook questions
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Chapter 2: Problem 2 Computer Organization and Design 5
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Chapter 2: Problem 2 Computer Organization and Design 5
For the following MIPS assembly instructions above, what is a corresponding C statement? add f, g, h add f, i, f
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Chapter 2: Problem 2 Computer Organization and Design 5
For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[ 8 ] = A[ i?j ] ;
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Chapter 2: Problem 2 Computer Organization and Design 5
For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll $t0, $s0, 2 # $t0 = f * 4 add $t0, $s6, $t0 # $t0 = &A[f] sll $t1, $s1, 2 # $t1 = g * 4 add $t1, $s7, $t1 # $t1 = &B[g] lw $s0, 0($t0) # f = A[f] addi $t2, $t0, 4 lw $t0, 0($t2) add $t0, $t0, $s0 sw $t0, 0($t1)
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Chapter 2: Problem 2 Computer Organization and Design 5
For the MIPS assembly instructions in Exercise 2.4, rewrite the assembly code to minimize the number if MIPS instructions (if possible) needed to carry out the same function.
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Chapter 2: Problem 2 Computer Organization and Design 5
The table below shows 32-bit values of an array stored in memory.
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Chapter 2: Problem 2 Computer Organization and Design 5
For the memory locations in the table above, write C code to sort the data from lowest to highest, placing the lowest value in the smallest memory location shown in the figure. Assume that the data shown represents the C variable called Array, which is an array of type int, and that the first number in the array shown is the first element in the array. Assume that this particular machine is a byte-addressable machine and a word consists of four bytes.
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Chapter 2: Problem 2 Computer Organization and Design 5
For the memory locations in the table above, write MIPS code to sort the data from lowest to highest, placing the lowest value in the smallest memory location. Use a minimum number of MIPS instructions. Assume the base address of Array is stored in register $s6.
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Chapter 2: Problem 2 Computer Organization and Design 5
Show how the value 0xabcdef12 would be arranged in memory of a little-endian and a big-endian machine. Assume the data is stored starting at address 0.
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Chapter 2: Problem 2 Computer Organization and Design 5
Translate 0xabcdef12 into decimal.
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Chapter 2: Problem 2 Computer Organization and Design 5
Translate the following C code to MIPS. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 4-byte words: B[ 8 ] = A[ i ] + A[ j ] ;
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Chapter 2: Problem 2 Computer Organization and Design 5
Translate the following MIPS code to C. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. addi $t0, $s6, 4 add $t1, $s6, $0 sw $t1, 0($t0) lw $t0, 0($t0) add $s0, $t1, $t0
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Chapter 2: Problem 2 Computer Organization and Design 5
For each MIPS instruction, show the value of the opcode (OP), source register (RS), and target register (RT) fields. For the I-type instructions, show the value of the immediate field, and for the R-type instructions, show the value of the destination register (RD) field.
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Chapter 2: Problem 2 Computer Organization and Design 5
Assume that registers $s0 and $s1 hold the values 0x80000000 and 0xD0000000, respectively.
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Chapter 2: Problem 2 Computer Organization and Design 5
What is the value of $t0 for the following assembly code? add $t0, $s0, $s1
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Chapter 2: Problem 2 Computer Organization and Design 5
Is the result in $t0 the desired result, or has there been overfl ow?
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Chapter 2: Problem 2 Computer Organization and Design 5
For the contents of registers $s0 and $s1 as specified above, what is the value of $t0 for the following assembly code? sub $t0, $s0, $s1
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Chapter 2: Problem 2 Computer Organization and Design 5
Is the result in $t0 the desired result, or has there been overflow?
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Chapter 2: Problem 2 Computer Organization and Design 5
For the contents of registers $s0 and $s1 as specified above, what is the value of $t0 for the following assembly code? add $t0, $s0, $s1 add $t0, $t0, $s0
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Chapter 2: Problem 2 Computer Organization and Design 5
Is the result in $t0 the desired result, or has there been overflow?
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Chapter 2: Problem 2 Computer Organization and Design 5
Assume that $s0 holds the value \(128_{\text{ten}}\).
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Chapter 2: Problem 2 Computer Organization and Design 5
For the instruction add $t0, $s0, $s1, what is the range(s) of values for $s1 that would result in overflow?
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Chapter 2: Problem 2 Computer Organization and Design 5
For the instruction sub $t0, $s0, $s1, what is the range(s) of values for $s1 that would result in overflow?
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Chapter 2: Problem 2 Computer Organization and Design 5
For the instruction sub $t0, $s1, $s0, what is the range(s) of values for $s1 that would result in overflow?
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Chapter 2: Problem 2 Computer Organization and Design 5
Provide the type and assembly language instruction for the following binary value: \(0000 \ 0010 \ 0001 \ 0000 \ 1000 \ 0000 \ 0010 \ 0000_{\text{two}}\)
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Chapter 2: Problem 2 Computer Organization and Design 5
Provide the type and hexadecimal representation of following instruction: sw $t1, 32($t2)
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Chapter 2: Problem 2 Computer Organization and Design 5
Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields: op=0, rs=3, rt=2, rd=3, shamt=0, funct=34
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Chapter 2: Problem 2 Computer Organization and Design 5
Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields: op=0x23, rs=1, rt=2, const=0x4
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Chapter 2: Problem 2 Computer Organization and Design 5
Assume that we would like to expand the MIPS register file to 128 registers and expand the instruction set to contain four times as many instructions.
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Chapter 2: Problem 2 Computer Organization and Design 5
How this would this affect the size of each of the bit fields in the R-type instructions?
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Chapter 2: Problem 2 Computer Organization and Design 5
How this would this affect the size of each of the bit fields in the I-type instructions?
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Chapter 2: Problem 2 Computer Organization and Design 5
How could each of the two proposed changes decrease the size of an MIPS assembly program? On the other hand, how could the proposed change increase the size of an MIPS assembly program?
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Chapter 2: Problem 2 Computer Organization and Design 5
Assume the following register contents: $t0 = 0xAAAAAAAA, $t1 = 0x12345678
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Chapter 2: Problem 2 Computer Organization and Design 5
For the register values shown above, what is the value of $t2 for the following sequence of instructions? sll $t2, $t0, 44 or $t2, $t2, $t1
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Chapter 2: Problem 2 Computer Organization and Design 5
For the register values shown above, what is the value of $t2 for the following sequence of instructions? sll $t2, $t0, 4 andi $t2, $t2, ?1
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Chapter 2: Problem 2 Computer Organization and Design 5
For the register values shown above, what is the value of $t2 for the following sequence of instructions? srl $t2, $t0, 3 andi $t2, $t2, 0xFFEF
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Chapter 2: Problem 2 Computer Organization and Design 5
Find the shortest sequence of MIPS instructions that extracts bits 16 down to 11 from register $t0 and uses the value of this field to replace bits 31 down to 26 in register $t1 without changing the other 26 bits of register $t1.
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Chapter 2: Problem 2 Computer Organization and Design 5
Provide a minimal set of MIPS instructions that may be used to implement the following pseudoinstruction: not $t1, $t2 // bit-wise invert
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Chapter 2: Problem 2 Computer Organization and Design 5
For the following C statement, write a minimal sequence of MIPS assembly instructions that does the identical operation. Assume $t1 = A, $t2 = B, and $s1 is the base address of C. A = C[ 0 ] << 4 ;
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Chapter 2: Problem 2 Computer Organization and Design 5
Assume $t0 holds the value 0x00101000. What is the value of $t2 aft er the following instructions? slt $t2, $0, $t0 bne $t2, $0, ELSE j DONE ELSE: addi $t2, $t2, 2 DONE:
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Chapter 2: Problem 2 Computer Organization and Design 5
Suppose the program counter (PC) is set to 0x2000 0000. Is it possible to use the jump (j) MIPS assembly instruction to set the PC to the address as 0x4000 0000? Is it possible to use the branch-on-equal (beq) MIPS assembly instruction to set the PC to this same address?
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Chapter 2: Problem 2 Computer Organization and Design 5
The following instruction is not included in the MIPS instruction set: rpt $t2, loop # if(R[rs]>0) R[rs]=R[rs]?1, PC=PC+4+BranchAddr
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Chapter 2: Problem 2 Computer Organization and Design 5
If this instruction were to be implemented in the MIPS instruction set, what is the most appropriate instruction format?
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Chapter 2: Problem 2 Computer Organization and Design 5
What is the shortest sequence of MIPS instructions that performs the same operation?
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Chapter 2: Problem 2 Computer Organization and Design 5
Consider the following MIPS loop: LOOP: slt $t2, $0, $t1 beq $t2, $0, DONE subi $t1, $t1, 1 addi $s2, $s2, 2 j LOOP DONE:
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Chapter 2: Problem 2 Computer Organization and Design 5
Assume that the register $t1 is initialized to the value 10. What is the value in register $s2 assuming $s2 is initially zero?
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Chapter 2: Problem 2 Computer Organization and Design 5
For each of the loops above, write the equivalent C code routine. Assume that the registers $s1, $s2, $t1, and $t2 are integers A, B, i, and temp, respectively.
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Chapter 2: Problem 2 Computer Organization and Design 5
For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed?
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Chapter 2: Problem 2 Computer Organization and Design 5
Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i, and j are in registers $s0, $s1, $t0, and $t1, respectively. Also, assume that register $s2 holds the base address of the array D. for( i = 0; i < a; i++) for( j=0; j < b; j++) D[ 4 * j ] = i + j ;
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Chapter 2: Problem 2 Computer Organization and Design 5
How many MIPS instructions does it take to implement the C code from Exercise 2.27? If the variables a and b are initialized to 10 and 1 and all elements of D are initially 0, what is the total number of MIPS instructions that is executed to complete the loop?
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Chapter 2: Problem 2 Computer Organization and Design 5
Translate the following loop into C. Assume that the C-level integer i is held in register $t1, $s2 holds the C-level integer called result, and $s0 holds the base address of the integer MemArray. addi $t1, $0, $0 LOOP: lw $s1, 0($s0) add $s2, $s2, $s1 addi $s0, $s0, 4 Addi $t1, $t1, 1 slti $t2, $t1, 100 bne $t2, $s0, LOOP
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Chapter 2: Problem 2 Computer Organization and Design 5
Rewrite the loop from Exercise 2.29 to reduce the number of MIPS instructions executed.
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Chapter 2: Problem 2 Computer Organization and Design 5
Implement the following C code in MIPS assembly. What is the total number of MIPS instructions needed to execute the function? int fib( int n ){ if ( n==0 ) return 0; else if ( n == 1 ) return 1; else return fib( n?1 ) + fib( n?2 );
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Chapter 2: Problem 2 Computer Organization and Design 5
Functions can often be implemented by compilers “in-line.” An in-line function is when the body of the function is copied into the program space, allowing the overhead of the function call to be eliminated. Implement an “in-line” version of the C code above in MIPS assembly. What is the reduction in the total number of MIPS assembly instructions needed to complete the function? Assume that the C variable n is initialized to 5.
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Chapter 2: Problem 2 Computer Organization and Design 5
For each function call, show the contents of the stack after the function call is made. Assume the stack pointer is originally at address 0x7ffffffc, and follow the register conventions as specified in Figure 2.11.
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Chapter 2: Problem 2 Computer Organization and Design 5
Translate function f into MIPS assembly language. If you need to use registers $t0 through $t7, use the lower-numbered registers first. Assume the function declaration for func is “int f(int a, int b);”. The code for function f is as follows: int f( int a, int b, int c, int d ){ return func( func ( a,b ),c+d ); }
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Chapter 2: Problem 2 Computer Organization and Design 5
Can we use the tail-call optimization in this function? If no, explain why not. If yes, what is the difference in the number of executed instructions in f with and without the optimization?
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Chapter 2: Problem 2 Computer Organization and Design 5
Right before your function f from Exercise 2.34 returns, what do we know about contents of registers $t5, $s3, $ra, and $sp? Keep in mind that we know what the entire function f looks like, but for function func we only know its declaration.
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Chapter 2: Problem 2 Computer Organization and Design 5
Write a program in MIPS assembly language to convert an ASCII number string containing positive and negative integer decimal strings, to an integer. Your program should expect register $a0 to hold the address of a null-terminated string containing some combination of the digits 0 through 9. Your program should compute the integer value equivalent to this string of digits, then place the number in register $v0. If a non-digit character appears anywhere in the string, your program should stop with the value ?1 in register $v0. For example, if register $a0 points to a sequence of three bytes 50ten, 52ten, 0ten (the null-terminated string “24”), then when the program stops, register $v0 should contain the value \(24_{\text{ten}}\).
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Chapter 2: Problem 2 Computer Organization and Design 5
Consider the following code: lbu $t0, 0( $t1 ) sw $t0, 0( $t2 ) Assume that the register $t1 contains the address 0x1000 0000 and the register $t2 contains the address 0x1000 0010. Note the MIPS architecture utilizes big-endian addressing. Assume that the data (in hexadecimal) at address 0x1000 0000 is: 0x11223344. What value is stored at the address pointed to by register $t2?
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Chapter 2: Problem 2 Computer Organization and Design 5
Write the MIPS assembly code that creates the 32-bit constant \(0010 \ 0000 \ 0000 \ 0001 \ 0100 \ 1001 \ 0010 \ 0100_{\text{two}}\) and stores that value to register $t1.
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Chapter 2: Problem 2 Computer Organization and Design 5
If the current value of the PC is 0x00000000, can you use a single jump instruction to get to the PC address as shown in Exercise 2.39?
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Chapter 2: Problem 2 Computer Organization and Design 5
If the current value of the PC is 0x00000600, can you use a single branch instruction to get to the PC address as shown in Exercise 2.39?
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Chapter 2: Problem 2 Computer Organization and Design 5
If the current value of the PC is 0x1FFFf000, can you use a single branch instruction to get to the PC address as shown in Exercise 2.39?
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Chapter 2: Problem 2 Computer Organization and Design 5
Write the MIPS assembly code to implement the following C code: lock( lk ); shvar=max( shvar,x ); unlock( lk ); Assume that the address of the lk variable is in $a0, the address of the shvar variable is in $a1, and the value of variable x is in $a2. Your critical section should not contain any function calls. Use ll/sc instructions to implement the lock( ) operation, and the unlock( ) operation is simply an ordinary store instruction.
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Chapter 2: Problem 2 Computer Organization and Design 5
Repeat Exercise 2.43, but this time use ll/sc to perform an atomic update of the shvar variable directly, without using lock( ) and unlock( ). Note that in this problem there is no variable lk.
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Chapter 2: Problem 2 Computer Organization and Design 5
Using your code from Exercise 2.43 as an example, explain what happens when two processors begin to execute this critical section at the same time, assuming that each processor executes exactly one instruction per cycle.
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Chapter 2: Problem 2 Computer Organization and Design 5
Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store instructions is 10, and the CPI of branch instructions is 3. Assume a program has the following instruction breakdowns: 500 million arithmetic instructions, 300 million load/store instructions, 100 million branch instructions.
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Chapter 2: Problem 2 Computer Organization and Design 5
Suppose that new, more powerful arithmetic instructions are added to the instruction set. On average, through the use of these more powerful arithmetic instructions, we can reduce the number of arithmetic instructions needed to execute a program by 25%, and the cost of increasing the clock cycle time by only 10%. Is this a good design choice? Why?
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Chapter 2: Problem 2 Computer Organization and Design 5
Suppose that we find a way to double the performance of arithmetic instructions. What is the overall speedup of our machine? What if we find a way to improve the performance of arithmetic instructions by 10 times?
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Chapter 2: Problem 2 Computer Organization and Design 5
Assume that for a given program 70% of the executed instructions are arithmetic, 10% are load/store, and 20% are branch.
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Chapter 2: Problem 2 Computer Organization and Design 5
Given this instruction mix and the assumption that an arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI.
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Chapter 2: Problem 2 Computer Organization and Design 5
For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?
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Chapter 2: Problem 2 Computer Organization and Design 5
For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?
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