A logic inverter is implemented using the arrangement of
Chapter 13, Problem 13.20(choose chapter or problem)
A logic inverter is implemented using the arrangement of Fig. 13.8 with switches having Ron = 1 k, VDD = 5 V, and (a) Find VOL, VOH, NML, and NMH. (b) If vI rises instantaneously from 0 V to +5 V and assuming the switches operate instantaneouslythat is, at t = 0,PU opens and PD closesfind an expression for vO(t), assuming that a capacitance C is connected between the output node and ground. Hence find the high-to-low propagation delay (tPHL) for C = 1 pF. Also find tTHL (see Fig. 13.15). (c) Repeat (b) for vI falling instantaneously from +5 V to 0 V. Again assume that PD opens and PU closes instantaneously. Find an expression for vO(t), and hence find tPLH and tTLH.
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