- 13.13.1: A particular logic inverter is specified to have VIL =1.2 V, VIH = ...
- 13.13.2: The voltage-transfer characteristic of a particular logic inverter ...
- 13.13.3: For a particular inverter design using a power supply VDD, VOL = 0....
- 13.13.4: A logic circuit family that used to be very popular is transistor-t...
- 13.13.5: Consider an inverter implemented as in Fig. 13.7(a). Let VDD = 5 V,...
- 13.13.6: For a logic-circuit family employing a 3-V supply, suggest an ideal...
- 13.13.7: For a particular logic-circuit family, the basic technology used pr...
- 13.13.8: A logic-circuit family intended for use in a digitalsignal-processi...
- 13.13.9: Design the inverter circuit in Fig. 13.2(a) to provide and so that ...
- 13.13.10: For the current-steering circuit in Fig. 13.9, , , find the values ...
- 13.13.11: Refer to the analysis of the resistive-load MOS inverter in Example...
- 13.13.12: Refer to the analysis of the resistive-load MOS inverter in Example...
- 13.13.13: Consider the saturated-load inverter of Fig. 13.11(a), analyzed in ...
- 13.13.14: Determining of the saturated-load inverter of Fig. 13.11(a) require...
- 13.13.15: It is required to design the saturated-load inverter in Fig. 13.11(...
- 13.13.16: An IC inverter fabricated in a 0.25-m CMOS process is found to have...
- 13.13.17: Consider a logic inverter of the type shown in Fig. 13.8. Let VDD =...
- 13.13.18: In a particular logic family, operating with a 3.3-V supply, the ba...
- 13.13.19: A collection of logic gates for which the static-power dissipation ...
- 13.13.20: A logic inverter is implemented using the arrangement of Fig. 13.8 ...
- 13.13.21: In a particular logic family, the standard inverter, when loaded by...
- 13.13.22: Consider an inverter for which tPLH, tPHL, tTLH, and tTHL are 20 ns...
- 13.13.23: A particular logic gate has tPLH and tPHL of 50 ns and 70 ns, respe...
- 13.13.24: We wish to investigate the design of the inverter shown in Fig. 13....
- 13.13.25: A logic-circuit family with zero static-power dissipation, normally...
- 13.13.26: Consider a CMOS inverter fabricated in a 0.25-m CMOS process for wh...
- 13.13.27: For the technology specified in 13.26, investigate the variation of...
- 13.13.28: For a technology in which show that the maximum current that the in...
- 13.13.29: A CMOS inverter for which and Vt = 0.5 V is connected as shown in F...
- 13.13.30: There are situations in which and of the CMOS inverter are delibera...
- 13.13.31: Consider the CMOS inverter of Fig. 13.17 with and matched and with ...
- 13.13.32: For a CMOS inverter fabricated in a 0.13-m process with , , , and h...
- 13.13.33: Consider a matched CMOS inverter fabricated in the 0.13-m process s...
- 13.13.34: For the CMOS inverter in Exercise 13.14 use the method of equivalen...
- 13.13.35: Use the method of equivalent resistance to determine the propagatio...
- 13.13.36: Use the method of equivalent resistance to design an inverter to be...
- 13.13.37: The method of average currents yields smaller values for and than t...
- 13.13.38: Find the propagation delay for a minimum-size inverter for which an...
- 13.13.39: A matched CMOS inverter fabricated in a process for which Cox = 3.7...
- 13.13.40: In this problem we investigate the effect of the selection of the r...
- 13.13.41: An inverter whose equivalent load capacitance C is composed of 10 f...
- 13.13.42: A CMOS microprocessor chip containing the equivalent of 1 million g...
- 13.13.43: Repeat 13.39 for an inverter for which Find tP and the dynamic powe...
- 13.13.44: In this problem we estimate the inverter power dissipation resultin...
- 13.13.45: Sketch a CMOS realization for the function
- 13.13.46: A CMOS logic gate is required to provide an output . How many trans...
- 13.13.47: Give two different realizations of the exclusive OR function in whi...
- 13.13.48: Sketch a CMOS logic circuit that realizes the function . This is ca...
- 13.13.49: Sketch a CMOS logic circuit that realizes the function .
- 13.13.50: It is required to design a CMOS logic circuit that realizes a three...
- 13.13.51: Give a CMOS logic circuit that realizes the function of three-input...
- 13.13.52: Design a CMOS full-adder circuit with inputs A, B, and C, and two o...
- 13.13.53: Consider the CMOS gate shown in Fig. 13.33. Specify ratios for all ...
- 13.13.54: Find appropriate sizes for the transistors used in the exclusive-OR...
- 13.13.55: Consider a four-input CMOS NAND gate for which the transient respon...
- 13.13.56: Figure P13.56 shows two approaches to realizing the OR function of ...
- 13.13.57: Consider the two-input CMOS NOR gate of Fig. 13.31 whose transistor...
- 13.13.58: A chip with a certain area designed using the 10-m process of the e...
- 13.13.59: Consider the scaling from a 0.18-m process to a 45-nm process.(a) A...
- 13.13.60: For a 0.18-m technology, for minimumlength NMOS devices is measured...
- 13.13.61: Consider NMOS and PMOS transistors with minimum channel length fabr...
- 13.13.62: (a) Show that for short-channel NMOS transistor, the ratio of the c...
- 13.13.63: (a) Consider a CMOS inverter fabricated in a deepsubmicron technolo...
- 13.13.64: (a) For a CMOS inverter fabricated in a deep-submicron technology w...
- 13.13.65: The current in the subthreshold conduction Eq. (13.102) is proporti...
- 13.13.66: An interconnect wire with a length L, a width W, and a thickness T ...

# Solutions for Chapter 13: Microelectronic Circuits 6th Edition

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ISBN: 9780195323030

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