Consider a four-input CMOS NAND gate for which the
Chapter 13, Problem 13.55(choose chapter or problem)
Consider a four-input CMOS NAND gate for which the transient response is dominated by a fixed-size capacitance between the output node and ground. Compare the values of tPLH and tPHL, obtained when the devices are sized as in Fig. 13.36, to the values obtained when all n-channel devices have = n and all p-channel devices have = p.
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