A matched CMOS inverter fabricated in a process for which
Chapter 13, Problem 13.39(choose chapter or problem)
A matched CMOS inverter fabricated in a process for which Cox = 3.7 fF/m2, nCox = 180 A/V2, pCox = 45 A/V2, = = 0.7 V, and VDD = 3.3 V, uses Wn = 0.75 m and Ln = Lp = 0.5 m. The overlap capacitance and the effective drainbody capacitance per micrometer of gate width are 0.4 fF and 1.0 fF, respectively. The wiring capacitance is Cw =2 fF. If the inverter is driving another identical inverter, find tPLH, tPHL, and tP. For how much additional capacitance load does the propagation delay increase by 50%?
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