A matched CMOS inverter fabricated in a process for which

A particular logic inverter is specified to have VIL =1.2 V, VIH = 1.5 V, VOL = 0.2 V, and VOH = 2.5 V. Find the high and low noise margins, NMH and NML.

The voltage-transfer characteristic of a particular logic inverter is modeled by three straight-line segments in the manner shown in Fig. 13.3. If VIL = 2.0 V, VIH = 2.5 V, VOL = 0.5 V, and VOH = 5 V, find: (a) The noise margins (b) The value of VM (c) The voltage gain in the transition region

For a particular inverter design using a power supply VDD, VOL = 0.1VDD, VOH = 0.8VDD, VIL = 0.4VDD, and VIH = 0.6VDD. What are the noise margins? What is the width of the transition region? For a minimum noise margin of 1 V, what value of VDD is required?

A logic circuit family that used to be very popular is transistor-transistor logic (TTL). The TTL logic gates and other building blocks are available commercially in smallscale integrated (SSI) and medium-scale-integrated (MSI) packages. Such packages can be assembled on printed-circuit boards to implement a digital system. The device data sheets provide the following specifications of the basic TTL inverter (of the SN7400 type): Logic-1 input level required to ensure a logic-0 level at the output: MIN (minimum) 2 V Logic-0 input level required to ensure a logic-1 level at the output: MAX (maximum) 0.8 V Logic-1 output voltage: MIN 2.4 V, TYP (typical) 3.3 V Logic-0 output voltage: TYP 0.22 V, MAX 0.4 V Logic-0-level supply current: TYP 3 mA, MAX 5 mA Logic-1-level supply current: TYP 1 mA, MAX 2 mA Propagation delay time to logic-0 level (tPHL): TYP 7 ns, MAX 15 ns Propagation delay time to logic-1 level (tPLH): TYP 11 ns, MAX 22 ns (a) Find the worst-case values of the noise margins. (b) Assuming that the inverter is in the 1-state 50% of the time and in the 0-state 50% of the time, find the average static power dissipation in a typical circuit. The power supply is 5 V. (c) Assuming that the inverter drives a capacitance CL =45 pF and is switched at a 1-MHz rate, use the formula in Eq. (13.35) to estimate the dynamic power dissipation. (d) Find the propagation delay tP.

Consider an inverter implemented as in Fig. 13.7(a). Let VDD = 5 V, R = 1.8 k, Ron = 200 , VIL = 1 V, and VIH = 2 V. (a) Find VOL, VOH, NMH, and NML. (b) The inverter is driving N identical inverters. Each of these load inverters, or fan-out inverters as they are usually called, is specified to require an input current of 0.2 mA when the input voltage (of the fan-out inverter) is high and zero current when the input voltage is low. Noting that the input currents of the fan-out inverters will have to be supplied through R of the driving inverter, find the resulting value of VOH and of NMH as a function of the number of fanout inverters N. Hence find the maximum value N can have while the inverter is still providing an NMH value approximately equal to its NML. (c) Find the static power dissipation in the inverter in the two cases: (i) the output is low, and (ii) the output is high and driving the maximum fan-out found in (b).

For a logic-circuit family employing a 3-V supply, suggest an ideal set of values for VM, VIL, VIH, VOL, VOH, NML, NMH. Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply?

For a particular logic-circuit family, the basic technology used provides an inherent limit to the smallsignal low-frequency voltage gain of 50 V/V. If, with a 3.3-V supply, the values of VOL and VOH are ideal, but = 0.4VDD, what are the best possible values of VIL and VIH that can be expected? What are the best possible noise margins you could expect? If the actual noise margins are only of these values, what VIL and VIH result? What is the large-signal voltage gain [defined as ]. (Hint: Use straight-line approximations for the VTC.)

A logic-circuit family intended for use in a digitalsignal-processing application in a newly developed hearing aid can operate down to single-cell supply voltages of 1.2 V. If for its inverter, the output signals swing between 0 and VDD, the gain-of-one points are separated by less than VDD, and the noise margins are within 30% of one another, what ranges of values of VIL, VIH, VOL, VOH, NML, and NMH can you expect for the lowest possible battery supply?

Design the inverter circuit in Fig. 13.2(a) to provide and so that the current drawn from the supply in the low-output state is 20 A. The transistor has , and . Specify the required values of , and W/L. How much power is drawn from the supply when the output is high? When the output is low?

For the current-steering circuit in Fig. 13.9, , , find the values of and to obtain a voltage swing of 1.5 V at each output. What are the values realized for and ?

Refer to the analysis of the resistive-load MOS inverter in Example 13.1 and utilize the expressions derived there for the various inverter parameters. Design the circuit to satisfy the following requirements: , and the power dissipation in the low-output state = 125 W. The transistor available has and Specify the required values of , , and W/L. What are the values obtained for , , , , and ?

Refer to the analysis of the resistive-load MOS inverter in Example 13.1 and utilize the expressions derived there for the various inverter parameters. For a technology for which , it is required to design the inverter to obtain . In terms of , what is the required value of the design parameter ? What values are obtained for , , , , , and , in terms of ? Give numerical values for the case . Now, express the power dissipated in the inverter in its lowoutput state in terms of the transistors W/L ratio. Let . If the power dissipation is to be limited to approximately 100 W, what W/L ratio is needed and what value of corresponds?

Consider the saturated-load inverter of Fig. 13.11(a), analyzed in Example 13.2. From Eq. (13.20), where is given by For , 0.8 V, use an iterative process to determine and By how much is reduced as a result of the body effect on ?

Determining of the saturated-load inverter of Fig. 13.11(a) requires a rather tedious process (see Example 13.2). An approximate estimate of can be obtained by reference to the VTC shown in Fig. 13.11(d). Specifically, when the straight-line segment BC is extrapolated, it meets the horizontal axis at which is usually close to the value of What is the approximate value obtained this way for the case analyzed in Example 13.2? How much does it differ from the value calculated the long way in Example 13.2?

It is required to design the saturated-load inverter in Fig. 13.11(a) for the case , , , and . Design for . Utilize the expressions derived in Example 13.2, except for use the following approximate expression (see Problem 13.11): Neglect the body effect in . Determine , , and for your design. Also determine and assuming that . What is the power dissipated in the inverter during its low-output state?

An IC inverter fabricated in a 0.25-m CMOS process is found to have a load capacitance of 10 fF. If the inverter is operated from a 2.5-V power supply, find the energy needed to charge and discharge the load capacitance. If the IC chip has 1 million of these inverters operating at an average switching frequency of 1 GHz, what is the power dissipated in the chip? What is the average current drawn from the power supply?

Consider a logic inverter of the type shown in Fig. 13.8. Let VDD = 5 V, and let a 1-pF capacitance be connected between the output node and ground. If the inverter is switched at the rate of 100 MHz, determine the dynamic power dissipation. What is the average current drawn from the dc power supply?

In a particular logic family, operating with a 3.3-V supply, the basic inverter draws (from the supply) a current of 40 A in one state and 0 A in the other. When the inverter is switched at the rate of 100 MHz, the average supply current becomes 150 A. Estimate the equivalent capacitance at the output node of the inverter.

A collection of logic gates for which the static-power dissipation is zero, and the dynamic-power dissipation is 10 mW is operating at 50 MHz with a 5-V supply. By what fraction could the power dissipation be reduced if operation at 3.3 V were possible? If the frequency of operation is reduced by the same factor as the supply voltage (i.e., ), what additional power can be saved

A logic inverter is implemented using the arrangement of Fig. 13.8 with switches having Ron = 1 k, VDD = 5 V, and (a) Find VOL, VOH, NML, and NMH. (b) If vI rises instantaneously from 0 V to +5 V and assuming the switches operate instantaneouslythat is, at t = 0, PU opens and PD closesfind an expression for vO(t), assuming that a capacitance C is connected between the output node and ground. Hence find the high-to-low propagation delay (tPHL) for C = 1 pF. Also find tTHL (see Fig. 13.15). (c) Repeat (b) for vI falling instantaneously from +5 V to 0 V. Again assume that PD opens and PU closes instantaneously. Find an expression for vO(t), and hence find tPLH and tTLH.

In a particular logic family, the standard inverter, when loaded by a similar circuit, has a propagation delay specified to be 1.2 ns: (a) If the current available to charge a load capacitance is half as large as that available to discharge the capacitance, what do you expect tPLH and tPHL to be? (b) If when an external capacitive load of 1 pF is added at the inverter output, its propagation delays increase by 70%, what do you estimate the normal combined capacitance of inverter output and input to be? (c) If without the additional 1-pF load connected, the load inverter is removed and the propagation delays were observed to decrease by 40%, estimate the two components of the capacitance found in (b) that is, the component due to the inverter output and other associated parasitics, and the component due to the input of the load inverter.

Consider an inverter for which tPLH, tPHL, tTLH, and tTHL are 20 ns, 10 ns, 30 ns, and 15 ns, respectively. The rising and falling edges of the inverter output can be approximated by linear ramps. Also, for simplicity, we define tTLH to be 0% to 100% (rather than 10% to 90%) rise time, and similarly for tTHL. Two such inverters are connected in tandem and driven by an ideal input having zero rise and fall times. Calculate the time taken for the output voltage to complete its excursion for (a) a rising input and (b) a falling input. What is the propagation delay for the inverter?

A particular logic gate has tPLH and tPHL of 50 ns and 70 ns, respectively, and dissipates 1 mW with output low and 0.5 mW with output high. Calculate the corresponding delaypower product (under the assumption of a 50% duty-cycle signal and neglecting dynamic power dissipation).

We wish to investigate the design of the inverter shown in Fig. 13.7(a). In particular, we wish to determine the value for R. Selection of a suitable value for R is determined by two considerations: propagation delay and power dissipation. (a) Show that if vI changes instantaneously from high to low and assuming that the switch opens instantaneously, the output voltage obtained across a load capacitance C will be where Hence show that the time required for vO(t) to reach the 50% point, is tPLH = 0.69CR (b) Following a steady state, if vI goes high and assuming that the switch closes immediately and has the equivalent circuit in Fig. 13.7(c), show that the output falls exponentially according to where . Hence show that the time for vO(t) to reach the 50% point is tPHL = 0.69CRon (c) Use the results of (a) and (b) to obtain the inverter propagation delay, defined as the average of tPLH and tPHL as (d) Show that for an inverter that spends half the time in the 0-state and half the time in the 1-state, the average static power dissipation is (e) Now that the trade-offs in selecting R should be clear, show that, for VDD = 5 V and C = 10 pF, to obtain a propagation delay no greater than 10 ns and a power dissipation no greater than 10 mW, R should be in a specific range. Find that range and select an appropriate value for R. Then determine the resulting values of tP and P.

A logic-circuit family with zero static-power dissipation, normally operates at VDD = 5 V. To reduce its dynamic-power dissipation operation at 3.3 V is considered. It is found, however, that the currents available to charge and discharge load capacitances also decrease. If current is (a) proportional to VDD or (b) proportional to , what reductions in maximum operating frequency do you expect in each case? What fractional change in delay power product do you expect in each case?

Consider a CMOS inverter fabricated in a 0.25-m CMOS process for which , and . In addition, and have L = 0.25 m and . (a) Find that results in . What is the silicon area utilized by the inverter in this case? (b) For the matched case in (a), find the values of , and (c) For the matched case in (a), find the output resistance of the inverter in each of its two states.

For the technology specified in Problem 13.26, investigate the variation of with the ratio . Specifically, calculate for (a) (the matched case); (b) (the minimum-size case); and (c) (a compromise case). For cases (b) and (c), estimate the approximate reduction in and silicon area relative to the matched case (a).

For a technology in which show that the maximum current that the inverter can sink while its low-output level does not exceed 0.1 is 0.075 For , find that permits this maximum current to be 0.5 mA

A CMOS inverter for which and Vt = 0.5 V is connected as shown in Fig. P13.29 to a sinusoidal signal source having a Thvenin equivalent voltage of 0.1-V peak amplitude and resistance of 100 k. What signal voltage appears at node A with vI = +1.5 V? With vI =1.5 V?

There are situations in which and of the CMOS inverter are deliberately mismatched to realize a certain desired value for . Show that the value required of the parameter r of Eq. (13.59) is given by For a 0.18-m process characterized by , , and , find the ratio required to obtain

Consider the CMOS inverter of Fig. 13.17 with and matched and with the input rising slowly from 0 to . At what value of does the current flowing through and reach its peak? Give an expression for the peak current, neglecting and For , , and , find the value of the peak

For a CMOS inverter fabricated in a 0.13-m process with , , , and having and , find , , and when the equivalent load capacitance C = 10 fF. Use the method of average currents.

Consider a matched CMOS inverter fabricated in the 0.13-m process specified in Problem 13.32. If C = 20 fF, use the method of average currents to determine the required (W/L) ratios so that .

For the CMOS inverter in Exercise 13.14 use the method of equivalent resistance to determine and 13

Use the method of equivalent resistance to determine the propagation delay of a minimum-size inverter, that is, one for which , designed in a 0.18-m technology. The equivalent load capacitance C = 10 fF.

Use the method of equivalent resistance to design an inverter to be fabricated in a 0.18-m technology. It is required that for C = 10 fF, and .

The method of average currents yields smaller values for and than those obtained by the method of equivalent resistances. Most of this discrepancy is due to the fact that the formula we derived for does not take into account velocity saturation. As will be seen in Section 13.5.2, velocity saturation reduces the current significantly. Using the results in Example 13.5, by what factor do you estimate the current reduction to be in the NMOS transistor? Since does not change, what do you conclude about the effect of velocity saturation on the PMOS transistor in this technology?

Find the propagation delay for a minimum-size inverter for which and ( )n = VDD = 3.3 V, Vtn = Vtp = 0.7 V, and the capacitance is roughly 2 fF/m of device width plus 1 fF/device. What does tP become if the design is changed to a matched one? Use the method of average current.

A matched CMOS inverter fabricated in a process for which Cox = 3.7 fF/m2, nCox = 180 A/V2, pCox = 45 A/V2, = = 0.7 V, and VDD = 3.3 V, uses Wn = 0.75 m and Ln = Lp = 0.5 m. The overlap capacitance and the effective drainbody capacitance per micrometer of gate width are 0.4 fF and 1.0 fF, respectively. The wiring capacitance is Cw =2 fF. If the inverter is driving another identical inverter, find tPLH, tPHL, and tP. For how much additional capacitance load does the propagation delay increase by 50%?

In this problem we investigate the effect of the selection of the ratio on the propagation delay of an inverter driving an identical inverter, as in Fig. 13.24. (a) Noting that except for each of the capacitances in Eqs. (13.72) and (13.73) is proportional to the width of the relevant transistor, show that C can be expressed as where is determined by the NMOS transistors. (b) Using the equivalent resistances and , show that for , (c) Use the results of (a) and (b) to determine in the case , in terms of and . (d) Use the results of (a) and (b) to determine in the matched case: that is, when is selected to yield . (e) Compare the values in (c) and (d) for the two extreme cases: (i) (ii) What do you conclude about the selection of

An inverter whose equivalent load capacitance C is composed of 10 fF contributed by the inverter transistors, and 20 fF contributed by the wiring and other external circuitry, has been found to have a propagation delay of 60 ps. By what factor must and be increased so as to reduce to 30 ps?

A CMOS microprocessor chip containing the equivalent of 1 million gates operates from a 5-V supply. The power dissipation is found to be 9 W when the chip is operating at 120 MHz, and 4.7 W when operating at 50 MHz. What is the power lost in the chip by some clock-independent mechanism, such as leakage and other static currents? If 70% of the gates are assumed to be active at any time, what is the average gate capacitance in such a design?

Repeat Problem 13.39 for an inverter for which Find tP and the dynamic power dissipation when the circuit is operated at a 250-MHz rate.

In this problem we estimate the inverter power dissipation resulting from the current pulse that flows in and when the input pulse has finite rise and fall times. Refer to Fig. 13.26 and let , and . Let the input rising and falling edges be linear ramps with the 0-to- and -to-0 transitions taking 1 ns each. Find To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from to , and the height equal to Also, determine the power dissipation that results when the inverter is switched at 100 MHz.

Sketch a CMOS realization for the function

A CMOS logic gate is required to provide an output . How many transistors does it need? Sketch a suitable PUN and PDN, obtaining each first independently, then one from the other using the dualnetworks idea.

Give two different realizations of the exclusive OR function in which the PDN and the PUN are dual networks.

Sketch a CMOS logic circuit that realizes the function . This is called the equivalence or coincidence function.

Sketch a CMOS logic circuit that realizes the function .

It is required to design a CMOS logic circuit that realizes a three-input, even-parity checker. Specifically, the output Y is to be low when an even number (0 or 2) of the inputs A, B, and C are high. (a) Give the Boolean function (b) Sketch a PDN directly from the expression for Note that it requires 12 transistors in addition to those in the inverters. (c) From inspection of the PDN circuit, reduce the number of transistors to 10. (d) Find the PUN as a dual of the PDN in (c), and hence the complete realization.

Give a CMOS logic circuit that realizes the function of three-input, odd-parity checker. Specifically, the output is to be high when an odd number (1 or 3) of the inputs are high. Attempt a design with 10 transistors (not counting those in the inverters) in each of the PUN and the PDN.

Design a CMOS full-adder circuit with inputs A, B, and C, and two outputs S and C0 such that S is 1 if one or three inputs are 1, and C0 is 1 if two or more inputs are 1.

Consider the CMOS gate shown in Fig. 13.33. Specify ratios for all transistors in terms of the ratios n and p of the basic inverter, such that the worst-case tPHL and tPLH of the gate are equal to those of the basic inverter.

Find appropriate sizes for the transistors used in the exclusive-OR circuit of Fig. 13.34(b). Assume that the basic inverter has and What is the total area, including that of the required inverters?

Consider a four-input CMOS NAND gate for which the transient response is dominated by a fixed-size capacitance between the output node and ground. Compare the values of tPLH and tPHL, obtained when the devices are sized as in Fig. 13.36, to the values obtained when all n-channel devices have = n and all p-channel devices have = p.

Figure P13.56 shows two approaches to realizing the OR function of six input variables. The circuit in Fig. P13.56(b), though it uses additional transistors, has in fact less total area and lower propagation delay because it uses NOR gates with lower fan-in. Assuming that the transistors in both circuits are properly sized to provide each gate with a current-driving capability equal to that of the basic matched inverter, find the number of transistors and the total area of each circuit. Assume the basic inverter to have a ( )n ratio of and a ( )p ratio of

Consider the two-input CMOS NOR gate of Fig. 13.31 whose transistors are properly sized so that the current-driving capability in each direction is equal to that of a matched inverter. For and VDD = 5 V, find the gate threshold in the cases for which (a) input terminal A is connected to ground and (b) the two input terminals are tied together. Neglect the body effect in QPB.

A chip with a certain area designed using the 10-m process of the early 1970s contains 10,000 transistors. What does Moores law predict the number of transistors to be on a chip of equal area fabricated using the 45-nm process of 2009?

Consider the scaling from a 0.18-m process to a 45-nm process. (a) Assuming and are scaled by the same factor as the device dimensions , find the factor by which the maximum operating speed, power density, and PDP decrease (or increase)? (b) Repeat (a) for the situation in which and are scaled by a factor of only 2.

For a 0.18-m technology, for minimumlength NMOS devices is measured to be 0.6 V and that for minimum-length PMOS devices 1.0 V. What do you estimate the effective values of and to be? Also find the values of for both device polarities.

Consider NMOS and PMOS transistors with minimum channel length fabricated in a 0.13-m CMOS process. If the effective values of and are 325 and 200 , respectively, find the expected values of for both device polarities.

(a) Show that for short-channel NMOS transistor, the ratio of the current obtained at to the current obtained if velocity saturation were absent is given by (b) Find the ratio in (a) for a transistor fabricated in a 0.13-m process with L = 0.13 m, , , and .

(a) Consider a CMOS inverter fabricated in a deepsubmicron technology utilizing transistors with the minimum allowed channel length and having an equivalent load capacitance C. Let rise instantaneously to and assume that turns off and turns on immediately. Ignoring channel-length modulation, that is, , and assuming operates in the velocity-saturation region, show that (b) Using the equivalent resistance of show that (c) If the formulas in (a) and (b) are to yield the same result, find for the NMOS transistor for a 0.13-m technology characterized by , , and

(a) For a CMOS inverter fabricated in a deep-submicron technology with = the minimum allowed channel length, it is required to select so that . This can be achieved by making of equal to of at Show that is given by (b) Find the required for a 0.13-m technology for which , , , and

The current in the subthreshold conduction Eq. (13.102) is proportional to . If the threshold voltage of an NMOS transistor is reduced by 0.1 V, by what factor will the static power dissipation increase? Repeat for a reduction in by 0.2 V. What do you conclude about the selection of a value of in process design?

An interconnect wire with a length L, a width W, and a thickness T has a resistance R given by where is the resistivity of the material of which the wire is made. The quantity is called the sheet resistance and has the dimension of ohms, although it is usually expressed as ohms/square or (refer to Fig. P13.66a). (a) Find the resistance of an aluminum wire that is 10 mm long and 0.5 m wide, if the sheet resistance is specified to be 27 . (b) If the wire capacitance to ground is 0.1 fF/m length, what is the total wire capacitance? (c) If we can model the wire very approximately as an RC circuit as shown in Fig. P13.66(b), find the delay time introduced by the wire. (Hint: .) (P.S. Only a small fraction of the interconnect on an IC would be this long!)