The transistor of Figure P12.32 has KP = 50 A/V2, W = 600

Give the equations for the drain current and the ranges of vGS, vDS, and vGD in terms of the threshold voltage Vto for each region (cutoff, saturation, and triode) of an n-channel MOSFET.

Sketch the physical structure of an nchannel enhancement MOSFET. Label the channel length L, the width W, the terminals, and the channel region. Draw the corresponding circuit symbol.

A certain NMOS transistor has Vto = 1 V, KP = 50 A/V2, L = 5 m, andW = 50 m. For each set of voltages, state the region of operation and compute the drain current. a. vGS = 4 V and vDS = 10 V; b. vGS = 4 V and vDS = 2 V; c. vGS = 0 V and vDS = 10 V.

Suppose that we have an NMOS transistor with KP = 50 A/V2,Vto = 1 V, L = 10 m, and W = 200 m. Sketch the drain characteristics for vDS ranging from 0 to 10 V and vGS = 0, 1, 2, 3, and 4 V.

Determine the values of Vto and K for the NMOS transistor having the characteristics shown in Figure P12.5. If KP = 50 A/V2, what is the value of W/L?

Suppose we have an NMOS transistor that has Vto = 1 V. What is the region of operation (linear, saturation, or cutoff) if: a. vGS = 0 V and vDS = 5 V; b. vGS = 4 V and vDS = 10 V; c. vGS = 3 V and vDS = 1 V; d. vGS = 3 V and vDS = 8 V?

Consider an n-channel enhancement MOSFET with Vto = 1 V and K = 0.2 mA/V2. Given that vGS = 3 V, for what range of vDS is the device in the saturation region? In the triode region? Plot iD versus vGS for operation in the saturation region.

Suppose that the gate of an enhancement NMOS device is connected to the drain. What is the region of operation if a positive voltage greater than the threshold voltage is applied to the drain/gate terminal with respect to the source? If the applied voltage is less than the threshold voltage?

Determine the region of operation for each of the enhancement transistors and the currents shown in Figure P12.9. All of the transistors have K = 0.2 mA/V2, the NMOS transistors have Vto= +1 V, and the PMOS transistors have Vto = 1 V. + 5 V Ia + 4 V (a) + + Ic 4 V 5 V (c) + Ib + 1 V 3 V (b) + 1 V Id + 3 V (d) Figure P12.9

The NMOS transistor shown in Figure P12.10 has KP = 50 A/V2, Vto = 1 V, L = 10 m, and W = 200 m. Determine the drain current if: a. R1 = 9 k and R2 = 1 k; b. R1 = 3 k and R2 = 2 k. R2

The PMOS transistor shown in Figure P12.11 has KP = 25 A/V2, Vto = 1 V, L = 10 m, and W = 200 m. Determine the drain current if: a. R1 = 1 k and R2 = 9 k; b. R1 = 3 k and R2 = 2 k. R2 R1 5 V + Figure P12.11 *P

Two points in the saturation region of a certain NMOS transistor are (vGS = 2 V, iD = 0.2 mA) and (vGS = 3 V, iD = 1.8 mA). Determine the values of Vto and K for this transistor.

A p-channel enhancement MOSFET has Vto = 0.5 V and K = 0.2 mA/V2. Assuming operation in the saturation region, what value of vGS is required for iD = 0.8 mA?

Suppose we need an NMOS transistor for which iD = 5 mA when vGS = vDS = 5 V. Process constraints result in KP = 50 A/V2 and Vto = 1 V. Determine the width-to-length ratio needed for the transistor. If L = 2 m, what is the value of W?

Because of process constraints, L andW are required to be at least 0.25 m. Furthermore, to save chip area, we do not want L or W to exceed 2 m. How should we select L and W to obtain the least drain current for a given transistor? The greatest drain current? Assuming operation with identical voltages, what ratio of drain currents (between different transistors) can be achieved?

Consider an NMOS transistor operating as a voltage-controlled resistance, as shown in Figure 12.4 on page 569, with vDS << vGS Vto. Find an approximate expression for the resistance of the channel in terms of the device parameters and voltages. Given Vto = 1 V and K = 0.2 mA/V2, compute the resistances for vGS = 1, 2, 3, and 4 V

Determine the currents and the region of operation for each of the enhancement transistors shown in Figure P12.17 for vin = 0 and for vin = 5 V. The transistors have |Vto| = 1 V and K = 0.4 mA/V2. (a) ia 5 V + + vin (b) ib 5 V + +

Given that the enhancement transistor shown in Figure P12.18 has Vto = 1 V and K = 0.5 mA/V2, find the value of the resistance R.

What is the principal cause of distortion in FET amplifiers?

Draw the load lines on the iDvDS axes for the circuit of Figure 12.10 on page 575 for: a. RD = 1 k and VDD = 20 V b. RD = 2 k and VDD = 20 V c. RD = 3 k and VDD = 20 V How does the position of the load line change as RD increases in value? P

Draw the load lines on the iDvDS axes for the circuit of Figure 12.10 on page 575 for: a. RD = 1 k and VDD = 5 V b. RD = 1 k and VDD = 10 V c. RD = 1 k and VDD = 15 V How does the position of the load line change as VDD increases in value? *

Consider the circuit shown in Figure 12.10 on page 575. The transistor characteristics are shown in Figure 12.11. Suppose thatVGG is changed to 0 V. Determine the values of VDSQ,VDSmin, and VDSmax. Find the gain of the amplifier.

Consider the amplifier shown in Figure P12.23. The characteristic curves for the transistor are shown in Figure P12.5. a. Find vGS(t), assuming that the coupling capacitor is a short circuit for the ac signal and an open circuit for dc. (Hint:Apply the superposition principle for the ac and dc sources.) b. Draw the load line for the amplifier on the characteristics. c. Find the values of VDSQ, VDSmin, and VDSmax.

What is the largest value of RD allowed in the circuit of Problem P12.23 if the instantaneous operating point is required to remain in the saturation region at all times?

Suppose that the resistance RD in Figure 12.10 (page 575) is replaced with an unusual two-terminal nonlinear device for which v = 0.1i 2 D, where iD is the current through the device in mA and v is the voltage across the device in volts (referenced positive at the end connected to VDD). Carefully sketch the load line on Figure 12.11 (page 576). What shape is this load line?

Use a load-line analysis of the circuit shown in Figure P12.26 to determine the values of VDSQ, VDSmin, and VDSmax. The characteristics of the FET are shown in Figure 12.21 on page 584. (Hint: First, replace the 15-V source and the resistances by theirThvenin equivalent circuit.) sin(vt) + + + 15 V 1.5 k 3 V 6 k Figure P12.26

Use a load-line analysis for the PMOS amplifier shown in Figure P12.27 to determine the maximum, minimum, and Qpoint values of vo(t). The characteristics of the transistor are shown in Figure 12.9 on page 574. iD 7 V 1 k sin (2000pt) + vo(t) + D G S + + 10 V Figure P12.27 P12.28. The distorted signa

The distorted signal shown in Figure 12.12(b) on page 576 can be written as vDS(t) = VDC + V1m sin(2000t) + V2m cos(4000t) The term V1m sin(2000t) is the desired signal. The term V2m cos(4000t) is distortion, which in this case has twice the frequency of the input signal, and is called secondharmonic distortion. Determine the values of V1m, V2m, and the percentage secondharmonic distortion, which is defined as |V2m/V1m| 100%. (A high-quality audio amplifier has a distortion percentage less than 0.1 percent.)

In an amplifier circuit, why do we need to bias the MOSFET at an operating point? What would happen if the input signal peak amplitude was smaller than 1 V, the transistor had Vto = 1 V, and we biased the transistor at VGSQ = 0?

Find IDQ and VDSQ for the circuit shown in Figure P12.30. The MOSFET has Vto = 1 V and K = 0.25 mA/V2. +15 V 15 V RD = 1 k RS = 3 k 1 M Figure P12.30

We need a fixed- plus self-bias circuit for an NMOS source follower with VDD = 12 V, RD = 0, and R1 = 1 M. The transistor has KP = 50A/V2, W = 800 m, L = 10 m, and Vto = 1 V. The circuit is to have VDSQ = 6 V and IDQ = 2 mA. Determine the values of R2 and RS.

The transistor of Figure P12.32 has KP = 50 A/V2, W = 600 m, L = 20 m, and Vto = 1 V. Determine the values of R1 and Rs. 1 M Rs 2 V + R1 2 k VG + 8 V + + 20 V Figure P12.32

Find IDQ and VDSQ for the circuit shown in Figure P12.33. The MOSFET has Vto = 1 V and K = 0.5 mA/V2. 4 k RD R2 100 k R1 150 k + 5 V Figure P12.33

Find IDQ and VDSQ for the circuit shown in Figure P12.34. The MOSFET has Vto = 1 V and K = 0.25 mA/V2. 1 k + 10 V Figure P12.34

The fixed- plus self-bias circuit of Figure 12.13 on page 578 has VDD = 12 V, R1 = 2 M, R2 = 1 M, RS = 2 k , and RD = 2 k. The MOSFET has Vto = 1 V and K = 0.5 mA/V2. Determine the Q point. P1

Determine the value of IDQ for the circuit shown in Figure P12.36, given that Vto = 1 V and K = 2 mA/V2. 1 k 1 M 3 M 1 k + 10 V Figure P12.36

Consider the fixed- plus self-bias circuit of Figure 12.13(a) on page 578, with VDD = 12 V, R1 = 1 M, and RD = 2 k. Nominally, the transistor has KP = 50 A/V2, W = 100 m, L = 10 m, and Vto = 1 V. The circuit is to have VDSQ = 6 V and IDQ = 1 mA. Determine the values needed for R2 and for RS.

Both transistors shown in Figure P12.38 have KP = 100 A/V2 and Vto = 1 V. Determine the value of R needed so that iD1 = 0.2 mA. For what range of Vx is the second transistor operating in the saturation region? What is the resulting value of iD2? Provided that Vx is large enough so that the second transistor operates in saturation, to what ideal circuit element is the transistor equivalent? + Vx +5 V = 4 R iD2 iD1 W2 L2 = 1 W1 L1 Figure P12.38

Give the definitions of gm and rd for a MOSFET as partial derivatives.

The characteristic curves of a certain NMOS transistor have constant values for iD in the saturation region. What is the value of rd, assuming operation in the saturation region?

Draw the small-signal equivalent circuit for a FET, including rd.

A certain NMOS transistor has the characteristics shown in Figure P12.42. Graphically determine the values of gm and rd at the operating point defined by VDSQ = 6 V and VGSQ = 2.5 V. 0 6.0 4.0 3.1 2.0 8.0 0 2 4 6 8 10 vDS (V) iD (mA) vGS = 3.0 6.4 mA 3.55 mA 1.5 mA 2.5 2.0 1.5 Figure P12.42

Consider an NMOS transistor that has gm = 1 mS and rd = 10 kW for a Q point of VGSQ = 1 V, IDQ = 2 mA, and VDSQ = 5 V. Sketch the drain characteristics to scale for a small region around the Q point, say for vGS = 0.8, 1.0, and 1.2V and for 4.0 < vDS < 6.0 V.

What is the value of gm for VDSQ = 0? Draw the small-signal equivalent circuit at this bias point. For what applications could the FET be used at this bias point?

Derive an expression for gm in terms of K, Vto,VGSQ, and IDQ for an NMOS transistor operating in the triode region

Derive an expression for rd in terms of K, Vto,VGSQ, and IDQ for an NMOS transistor operating in the triode region.

Consider an unusual type of FET for which iD = 0.2vDS + 4v2 GS, in which iD is in mA, vGS is in volts, and vDS is in volts. Determine the values of gm and rd for a Q point of VGSQ = 2 V and VDSQ = 10 V

Consider an unusual type of FET for which iD = exp(vGS) + 0.02v2 DS, in which iD is in mA,vGS is in volts, and vDS is in volts. Determine the values of gm and rd for a Q point of VGSQ = 1 V and VDSQ = 10 V.

A certain NMOS transistor has vGS(t) = 1 V vDS(t) = 4 + 0.5 sin(t) V iD(t) = 6 + 0.01 sin(t) mA Which small-signal parameter (gm orrd) can be determined from this information?What is its value? For what Q point (VGSQ, IDQ, and VDSQ) does this parameter apply?

A certain NMOS transistor has vGS(t) = 2 + 0.2 sin(t) V vDS(t) = 5 V iD(t) = 1 + 0.2 sin(t) mA Which small-signal parameter (gm orrd) can be determined from this information?What is its value? For what Q point (VGSQ, IDQ, and VDSQ) does this parameter apply?

Draw the circuit diagram of a resistance capacitance coupled common-source ampli- fier.

Explain the function of coupling capacitors. Assuming that they are performing their intended function, how do they appear in the ac equivalent circuit? In general, what effect do coupling capacitors have on the gain of an amplifier as a function of frequency?

Consider the common-source amplifier shown in Figure P12.53. The NMOS transistor has KP = 50 A/V2, L = 5 m, W = 500 m,Vto = 1 V, and rd = . RL = 1 k R1 RD = 1 k +20 V 1.7 M vo + vin + R2 300 k Figure P12.53 Problems 605 a. Determine the values of IDQ, VDSQ, and gm. b. Compute the voltage gain, input resistance, and output resistance, assuming that the coupling capacitors are short circuits for the ac signal.

Repeat Problem P12.53 for an NMOS transistor having KP = 50 A/V2,W = 600 m, L = 20 m, Vto = 2 V, and rd = . Compare the gain with that attained in Problem P12.53.

Consider the amplifier shown in Figure P12.55. a. Draw the small-signal equivalent circuit, assuming that the capacitors are short circuits for the signal. b. Assume that rd = , and derive expressions for the voltage gain, input resistance, and output resistance. c. Find IDQ if R = 100 k, Rf = 100 k, RD = 3 k, RL = 10 k, VDD = 20 V, Vto = 5 V, and K = 1 mA/V2. Determine the value of gm at the Q point. d. Evaluate the expressions found in part (b) using the values given in part (c). e. Find vo(t) if v(t) = 0.2 sin(2000t). f. Is this amplifier inverting or noninverting? ii

Find VDSQ and IDQ for the FET shown in Figure P12.56, given Vto = 3 V and K = 0.5 mA/V2. Find the value of gm at the operating point. Draw the small-signal equivalent circuit, assuming that rd = . Derive an expression for the resistance Ro in terms of RD and gm. Evaluate the expression for the values given.

Consider the common-source amplifier and the source follower. Which amplifier would be used if a voltage-gain magnitude larger than unity is needed? Which would be used to obtain low output resistance?

Draw the circuit diagram of a resistance capacitance coupled source follower.

Consider the source follower shown in Figure 12.26 on page 589, given VDD = 15 V, RL = 2 k, R1 = 1 M, and R2 = 2 M. The NMOS transistor has KP = 50 A/V2, L = 10 m,W = 160 m,rd = , and Vto = 1 V. Find the value for RS to achieve IDQ = 2 mA.Then, compute the voltage gain, input resistance, and output resistance. P

Consider the common-gate amplifier of Figure 12.29 on page 592, which was analyzed in Exercise 12.13 on page 592. The MOSFET has KP = 50 A/V2,W = 600 m, L = 10 m,Vto = 1 V, and rd = . The supply voltages areVDD = 15 V andVSS = 15 V. The resistances are RS = 3 k, RL = 10 k, and RD = 3 k. a. Determine the Q point and the value of gm. b. Determine the input resistance and the voltage gain. S

Draw the circuit diagram of a CMOS inverter. Draw its equivalent circuit (open and closed switches) if the input is high. Repeat if the input is low

Draw the circuit diagram of a two-input CMOS AND gate. (Hint: Use a two-input NAND followed by an inverter.)

a. Draw the circuit diagram of a three-input CMOS NAND gate. b. Draw its equivalent circuit (open and closed switches) if all three inputs are high. c. Repeat if all three inputs are low

Consider the simple model for a CMOS inverter shown in Figure P12.64. Each transistor has been modeled by a switch in series with a resistance, and the input to the gates driven by the inverter is modeled as a load capacitance CL. The output cycles from high to low and back to high at a frequency f. a. Find an expression for the average power taken from the VDD source. Where is this power dissipated? b. If VDD is cut in half, by how much is the power reduced? c. Suppose we have computer chip withVDD = 1V, a clock frequency of 1 GHz, and 1 billion gates, each of which cycles between states at an average rate equal to 1% of the clock frequency. Also, the average capacitive load for each gate is 2 fF. (Note: 1 fF = 1 femtofarad = 1015 F.) Compute the average power consumed by this chip