(a) Assume the inverters have a delay of 1 ns and the
Chapter 8, Problem 8.6(choose chapter or problem)
(a) Assume the inverters have a delay of 1 ns and the other gates have a delay of 2 ns. Initially A = B = C = 0 and D = 1; C changes to 1 at time 2 ns. Draw a timing diagram showing the glitch corresponding to the hazard.
(b) Modify the circuit so that it is hazard free. (Leave the circuit as a two-level, OR- AND circuit.)
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