Fundamentals of Logic Design 7th Edition solutions

Fundamentals of Logic Design 7
A bank vault has three locks with a different key for each lock. Each key is owned by a different person. To open the door, at least two people must insert their keys into the assigned locks. The signal lines A, B, and C are 1 if there is a key inserted into lock 1, 2, or 3, respectively. Write an eq

Fundamentals of Logic Design 7
Make a circuit which gives the absolute value of a 4-bit binary number. Use four full adders, four multiplexers, and four inverters. Assume negative numbers are represented in 2s complement. Recall that one way to find the 2s complement of a binary number is to invert all of the bits and then add 1.

Fundamentals of Logic Design 7
Convert to hexadecimal and then to binary: (a) \(757.25_{10}\) (b) \(123.17_{10}\) (c) \(356.89_{10}\) (d) \(1063.5_{10}\)

Fundamentals of Logic Design 7
Design a decade counter using the excess-3 code for decimal digits. Use NAND gates and the indicated flip-flop types. (a) Use D flip-flops. (b) Use J-K flip-flops. (c) Use T flip-flops. (d) Use S-R flip-flops.

Fundamentals of Logic Design 7
Add, subtract, and multiply in binary: (a) 1111 and 1010 (b) 110110 and 11101 (c) 100100 and 10110

Fundamentals of Logic Design 7
A latch can be constructed from an OR gate, an AND gate, and an inverter connected as follows: (a) What restriction must be placed on R and H so that P will always equal \(Q^\prime\) (under steady-state conditions)? (b) Construct a next-state table and derive the ch

Fundamentals of Logic Design 7
Convert to base \(\text { 6: 3??.}25_{14}\) (do all of the arithmetic in decimal).

Fundamentals of Logic Design 7
A switching circuit has two control inputs (\(C_1\) and \(C_2\)), two data inputs (\(X_1\) and \(X_2\)), and one output (Z). The circuit performs logic operations on the two data inputs, as shown in this table: (a) Derive a truth table for Z. (b) Use a Karnaugh map to find a minimum

Fundamentals of Logic Design 7
Realize a BCD to excess-3 code converter using a 4-to-10 decoder with active low outputs and a minimum number of gates.

Fundamentals of Logic Design 7
An L-M flip-flop works as follows: If LM = 00, the next state of the flip-flop is 1. If LM = 01, the next state of the flip-flop is the same as the present state. If LM = 10, the next state of the flip-flop is the complement of the present state. If LM = 11, the next state of the flip

Fundamentals of Logic Design 7
Design a circuit which will either subtract X from Y or Y from X, depending on the value of A. If A = 1, the output should be X ? Y, and if A = 0, the output should be Y ? X. Use a 4-bit subtracter and two 4-bit 2-to-1 multiplexers (with bus inputs and outputs as in Figure 9-7).

Fundamentals of Logic Design 7
Construct a table for 4-3-2-1 weighted code and write 9154 using this code.

Fundamentals of Logic Design 7
Construct a transition graph for the shift register shown. (X is the input, and Z is the output.) Is this a Mealy or Moore machine?

Fundamentals of Logic Design 7
(a) If the ROM in the hexadecimal to ASCII code converter of Figure 9-26 is replaced with a PAL, give the internal connection diagram. (b) If the same ROM is replaced with a PLA, give the PLA table.

Fundamentals of Logic Design 7
Show how to implement a full subtracter using a PAL. See Figure 9-33.

Fundamentals of Logic Design 7
Construct a 6-2-2-1 weighted code for decimal digits. What number does 1100 0011 represent in this code?

Fundamentals of Logic Design 7
Find eight different simplified two-level gate circuits to realize (a) \(F(w, x, y, z)=\left(x+y^{\prime}+z\right)\left(x^{\prime}+y+z\right) w\) (b) \(F(a, b, c, d)=\Sigma m(4,5,8,9,13)\)

Fundamentals of Logic Design 7
(a) Implement the following function using only 2-to-1 MUXes: \(R = ab^\prime h^\prime + bch^\prime + eg^\prime h + fgh\). (b) Repeat using only tri-state buffers.

Fundamentals of Logic Design 7
A logic circuit realizing the function f has four inputs A, B, C, and D. The three inputs A, B, and C are the binary representation of the digits 0 through 7 with A being the most-significant bit. The input D is an odd-parity bit, i.e., the value of D is such that A, B, C, and D always contain an odd

Fundamentals of Logic Design 7
The circuit below has a 4-input priority encoder connected to a 2-to-4 decoder with enable. The truth table for the priority encoder is given. (The \(I_3\) input is highest priority.) All signals are active high. What functions of A, B, C, and D are realized by \(Z_3\), \(Z_2\), \(Z_1\), and \(Z_0\)?