Write a VHDL module that finds the average value of four
Chapter 10, Problem 10.7(choose chapter or problem)
Write a VHDL module that finds the average value of four 16-bit unsigned numbers that are represented by std_logic_vectors. Division by four is best accomplished by shifting. Round off your answer to the nearest integer.
Unfortunately, we don't have that question answered yet. But you can get it answered in just 5 hours by Logging in or Becoming a subscriber.
Becoming a subscriber
Or look for another answer