In the following circuit, all gates, including the
Chapter 10, Problem 10.19(choose chapter or problem)
In the following circuit, all gates, including the inverter, have an inertial delay of 10 ns.
(a) Write VHDL code that gives a dataflow description of the circuit. All delays should be inertial delays.
(b) Using the Direct VHDL simulator simulate the circuit. (Use a View Interval of 100 ns.) Initially set A = 1, B = 1 and C = 1, then run the simulator for 40 ns. Change B to 0, and run the simulator for 40 ns. Record the waveform.
(c) Change the VHDL code of part (a) so that the inverter has a delay of 5 ns.
(d) Repeat part (b).
(e) Change the VHDL code of part (c) so that the output OR gate has a transport delay rather than an inertial delay.
(f ) Repeat part (b).
(g) Explain any differences between the waveforms for parts (b), (d), and (f).
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