Write a VHDL module for a 4-bit comparator. The comparator
Chapter 17, Problem 17.14(choose chapter or problem)
Write a VHDL module for a 4-bit comparator. The comparator has two inputs, A and B, which are 4-bit std_logic vectors; and three std_logic outputs, AGB, ALB, and AEB. AGB = '1' if A is greater than B, ALB = '1' if A is less than B, ALB = '1' if A and B are equal.
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