Solution: The circuit shown in Figure SP 10-1 has two inputs, vs(t) and is(t), and one

Chapter 10, Problem SP10-3

(choose chapter or problem)

The circuit shown in Figure SP 10-1 has two inputs, \(v_{\mathrm{s}}(t)\) and \(i_{\mathrm{s}}(t)\), and one output, v(t). The inputs are given by

                                                              \(v_{\mathrm{s}}(t)=10 \sin \left(6 t+45^{\circ}\right) \mathrm{V}\)

and

                                                                          \(i_s(t)=0.8 \mathrm{~A}\)

Use PSpice to demonstrate superposition. Simulate three versions of the circuit simultaneously. (Draw the circuit in the PSpice workspace. Cut and paste to make two copies. Edit the part names in the copies to avoid duplicate names. For example, the resistor will be R1 in the original circuit. Change R1 to R2 and R3 in the two copies.) Use the given \(v_s(t)\) and \(i_s(t)\) in the first version. Set \(i_{\mathrm{s}}(t)=0\) in the second version and \(v_{\mathrm{s}}(t)=0\) in the third version. Plot the capacitor voltage v(t) for all three versions of the circuit. Show that the capacitor voltage in the first version of the circuit is equal to the sum of the capacitor voltages in the second and third versions.

Hint: Use PSpice parts VSIN and IDC for the voltage and current source. PSpice uses hertz rather than rad / s as the unit for frequency.

Remark: Notice that v(t) looks sinusoidal, but it's not sinusoidal because of the dc offset.