For a particular depletion-mode NMOS device, V, A/V2, and

MOS technology is used to fabricate a capacitor, utilizing the gate metallization and the substrate as the capacitor electrodes. Find the area required per 1-pF capacitance for oxide thickness ranging from 2 nm to 10 nm. For a square plate capacitor of 10 pF, what dimensions are needed?

Calculate the total charge stored in the channel of an NMOS transistor having fF/m2, L = 0.25 m, and W = 2.5 m, and operated at V and V.

Use dimensional analysis to show that the units of the process transconductance parameter are A/V2. What are the dimensions of the MOSFET transconductance parameter kn?

An NMOS transistor that is operated with a small is found to exhibit a resistance . By what factor will change in each of the following situations? (a) is doubled. (b) The device is replaced with another fabricated in the same technology but with double the width. (c) The device is replaced with another fabricated in the same technology but with both the width and length doubled. (d) The device is replaced with another fabricated in a more advanced technology for which the oxide thickness is halved and similarly for W and L (assume n remains unchanged).

An NMOS transistor fabricated in a technology for which A/V2 and V is required to operate with a small as a variable resistor ranging in value from 200 to 1 k . Specify the range required for the control voltage and the required transistor width W. It is required to use the smallest possible device, as limited by the minimum channel length of this technology ( m) and the maximum allowed voltage of 1.8 V.

Sketch a set of characteristic curves for an NMOS transistor operating with a small (in the manner shown in Fig. 5.4). Let the MOSFET have mA/V2 and V. Sketch and clearly label the graphs for , 1.0, 1.5, 2.0, and 2.5 V. Let be in the range 0 to 50 mV. Give the value of obtained for each of the five values of . Although only a sketch, your diagram should be drawn to scale as much as possible.

An n-channel MOS device in a technology for which oxide thickness is 20 nm, minimum channel length is 1 m, and Vt = 0.8 V operates in the triode region, with small vDS and with the gatesource voltage in the range 0 V to +5 V. What device width is needed to ensure that the minimum available resistance is 1 k?

Consider an NMOS transistor operating in the triode region with an overdrive voltage . Find an expression for the incremental resistance Give the values of in terms of and for , 0.5 , 0.8 , and .

An NMOS transistor with mA/V2 and V is operated with V. At what value of does the transistor enter the saturation region? What value of is obtained in saturation?

Consider a CMOS process for which Lmin = 0.25 m, tox = 6 nm, n = 460 cm2/Vs, and Vt = 0.5 V. (a) Find Cox and (b) For an NMOS transistor with W/L = 15 m/0.25 m, calculate the values of VOV, VGS, and VDSmin needed to operate the transistor in the saturation region with a dc current ID = 0.8 mA. (c) For the device in (b), find the value of VOV and VGS required to cause the device to operate as a 500- resistor for very small vDS.

A p-channel MOSFET with a threshold voltage V has its source connected to ground. (a) What should the gate voltage be for the device to operate with an overdrive voltage of V? (b) With the gate voltage as in (b), what is the highest voltage allowed at the drain while the device operates in the saturation region? (c) If the drain current obtained in (b) is 1 mA, what would the current be for mV and for

With the knowledge that p  0.4 n, what must be the relative width of n-channel and p-channel devices if they are to have equal drain currents when operated in the saturation mode with overdrive voltages of the same magnitude?

An n-channel device has Vt = 0.8 V, and W/L = 20. The device is to operate as a switch for small vDS, utilizing a control voltage vGS in the range 0 V to 5 V. Find the switch closure resistance, rDS, and closure voltage, VDS, obtained when vGS = 5 V and iD = 1 mA. Recalling that p  0.4 n, what must W/L be for a p-channel device that provides the same performance as the n-channel device in this application?

Consider an n-channel MOSFET with tox = 9 nm, n = 500 cm2/Vs, Vt = 0.7 V, and W/L = 10. Find the drain current in the following cases: (a) vGS = 5 V and vDS = 1 V (b) vGS = 2 V and vDS = 1.3 V (c) vGS = 5 V and vDS = 0.2 V (d) vGS = vDS = 5 V

This problem illustrates the central point in the electronics revolution that has been in effect for the past four decades: By continually reducing the MOSFET size, we are able to pack more devices on an IC chip. Gordon Moore, co-founder of Intel Corporation, predicted this exponential growth of chip-packing density very early in the history of the development of the integrated circuit in the formulation that has become known as Moores law. The table below shows four technology generations, each characterized by the minimum possible MOSFET channel length (row 1). In going from one generation to another, both L and are scaled by the same factor. The power supply utilized is also scaled by the same factor, to keep the magnitudes of all electrical fields within the device unchanged. Unfortunately, but for good reasons, cannot be scaled similarly. Complete the table entries, noting that row 5 asks for the transconductance parameter of an NMOS transistor with W/L = 10; row 9 asks for the value of obtained with ; row 10 asks for the power dissipated in the circuit. An important quantity is the power density, P/A, asked for in row 11. Finally, you are asked to find the number of transistors that can be placed on an IC chip fabricated in each of the technologies in terms of the number obtained with the 0.5-m technology (n). In the following problems, when is not specified, assume it is zero.

Show that when channel-length modulation is neglected (i.e., ), plotting versus for various values of , and plotting versus for , results in universal representation of the and characteristics of the NMOS transistor. That is, the resulting graphs are both technology and device independent. Furthermore, these graphs apply equally well to the PMOS transistor by a simple relabeling of variables. (How?) What is the slope at of each of the versus graphs? For the versus graph, find the slope at a point vOV = VOV.

An NMOS transistor having Vt = 1 V is operated in the triode region with vDS small. With VGS = 1.5 V, it is found to have a resistance rDS of 1 k. What value of VGS is required to obtain rDS = 200 ? Find the corresponding resistance values obtained with a device having twice the value of W.

A particular enhancement MOSFET for which Vt = 0.5 V and (W/L) = 0.1 mA/V2 is to be operated in the saturation region. If iD is to be 12.5 A, find the required vGS and the minimum required vDS. Repeat for iD = 50 A.

A particular n-channel enhancement MOSFET is measured to have a drain current of 0.4 mA at VGS = VDS = 2 V and of 0.1 mA at VGS = VDS = 1.5 V. What are the values of and Vt for this device?

For a particular IC-fabrication process, the transconductance parameter = 400 A/V2, and Vt = 0.4 V. In an application in which vGS = vDS = Vsupply = 1.8 V, a drain current of 2 mA is required of a device of minimum length of 0.18m. What value of channel width must the design use?

For a particular IC-fabrication process, the transconductance parameter = 400 A/V2, and Vt = 0.4 V. In an application in which vGS = vDS = Vsupply = 1.8 V, a drain current of 2 mA is required of a device of minimum length of 0.18m. What value of channel width must the design use?

For an NMOS transistor, for which Vt = 0.5 V, operating with vGS in the range of 0.8 V to 1.8 V, what is the largest value of vDS for which the channel remains continuous?

An NMOS transistor, fabricated with W = 100 m and L = 5 m in a technology for which = 50 A/V2 and Vt = 1 V, is to be operated at very low values of vDS as a linear resistor. For vGS varying from 1.1 V to 11 V, what range of resistor values can be obtained? What is the available range if (a) the device width is halved? (b) the device length is halved? (c) both the width and length are halved?

When the drain and gate of a MOSFET are connected together, a two-terminal device known as a diode-connected transistor results. Figure P5.24 shows such devices obtained from MOS transistors of both polarities. Show that (a) the iv relationship is given by (b) the incremental resistance r for a device biased to operate at is given by

For the circuit in Fig. P5.25, sketch versus for varying from 0 to . Clearly label your sketch

For the circuit in Fig. P5.26, find an expression for in terms of . Sketch and clearly label a graph for versus

The table below lists 10 different cases labeled (a) to (j) for operating an NMOS transistor with V. In each case the voltages at the source, gate, and drain (relative to the circuit ground) are specified. You are required to complete the table entries. Note that if you encounter a case for which is negative, you should exchange the drain and source before solving the problem. You can do this because the MOSFET is a symmetric device.

The NMOS transistor in Fig. P5.28 has V and . Sketch and clearly label versus with varying in the range 0 to V. Give equations for the various portions of the resulting graph.

Fig. P5.29 shows two NMOS transistors operating in saturation at equal and . (a) If the two devices are matched except for a maximum possible mismatch in their W/L ratios of 2%, what is the maximum resulting mismatch in the drain currents? (b) If the two devices are matched except for a maximum possible mismatch in their values of 10 mV, what is the maximum resulting mismatch in the drain currents? Assume that the nominal value of is 1 V.

For a particular MOSFET operating in the saturation region at a constant vGS, iD is found to be 1 mA for vDS = 1 V and 1.05 mA for vDS = 2 V. What values of ro, VA, and

A particular MOSFET has VA = 50 V. For operation at 0.1 mA and 1 mA, what are the expected output resistances? In each case, for a change in vDS of 1 V, what percentage change in drain current would you expect?

In a particular IC design in which the standard channel length is 2 m, an NMOS device with W/L of 5 operating at 100 A is found to have an output resistance of 0.5 M, about of that needed. What dimensional change can be made to solve the problem? What is the new device length? The new device width? The new W/L ratio? What is VA for the standard device in this IC? The new device?

For a particular n-channel MOS technology, in which the minimum channel length is 1 m, the associated value of is 0.02 V1. If a particular device for which L is 3m operates at vDS = 1 V with a drain current of 80 A, what does the drain current become if vDS is raised to 5 V? What percentage change does this represent? What can be done to reduce the percentage by a factor of 2?

An NMOS transistor is fabricated in a 0.8-m process having = 130 A/V2 and = 20 V/m of channel length. If L = 1.6 m and W = 16 m, find VA and . Find the value of ID that results when the device is operated with an overdrive voltage of 0.5 V and VDS = 2 V. Also, find the value of ro at this operating point. If VDS is increased by 1 V, what is the corresponding change in ID?

If in an NMOS transistor, both W and L are quadrupled and is halved, by what factor does change?

Consider the circuit in Fig. P5.29 with both transistors perfectly matched but with the dc voltage at the drain of lowered to V. If the two drain currents are to be matched within 1% (i.e., the maximum difference allowed between the two currents is 1%), what is the minimum required value of ? If the technology is specified to have V/m, what is the minimum channel length the designer must use?

Complete the missing entries in the following table, which describes characteristics of suitably biased NMOS transistors:

An enhancement PMOS transistor has = Vt = 1.5 V, and = 0.02 V1. The gate is connected to ground and the source to +5 V. Find the drain current for vD = +4 V, +1.5 V, 0 V, and 5 V.

A p-channel transistor for which and 50 V operates in saturation with 4 V, and iD = 3 mA. Find corresponding signed values for vGS, vSG, vDS, vSD, Vt, VA,

The table below lists the terminal voltages of a PMOS transistor in six cases, labeled a, b, c, d, e, and f. The transistor has . Complete the table entries.

The PMOS transistor in Fig. P5.41 has V. As the gate voltage is varied from V to 0 V, the transistor moves through all of its three possible modes of operation. Specify the value of at which the device changes modes of operation.

(a) Using the expression for iD in saturation and neglecting the channel-length modulation effect (i.e., let =0), derive an expression for the per unit change in iD per C in terms of the per unit change in per C , the temperature coefficient of Vt in V/C and VGS and Vt. (b) If Vt decreases by 2 mV for every C rise in temperature, find the temperature coefficient of that results in iD decreasing by 0.2%/C when the NMOS transistor with Vt = 1 V is operated at VGS = 5 V.

Various NMOS and PMOS transistors, numbered 1 to 4, are measured in operation, as shown in the table at the bottom of the page. For each transistor, find the value of CoxW/L and Vt that apply and complete the table, with V in volts, I in A, and

All the transistors in the circuits shown in Fig. P5.44 have the same values of , W/L, and . Moreover, is negligibly small. All operate in saturation at ID = I and Find the voltages V1, V2, V3, and V4. If and I = 0.1 mA, how large a resistor can be inserted in series with each drain connection while maintaining saturation? What is the largest resistor that can be placed in series with each gate? If the current source I requires at least 0.5 V between its terminals to operate properly, what is the largest resistor that can be placed in series with each MOSFET source while ensuring saturatedmode operation of each transistor at ID = I? In the latter limiting situation, what do V1, V2, V3, and V4 become? Note: If is not specified, assume it is zero.

Design the circuit of Fig. 5.21 to establish a drain current of 0.25 mA and a drain voltage of 0 V. The MOSFET has Vt = 1 V, nCox = 60 A/V2, L = 3 m, and W = 100 m.

For the circuit in Fig. E5.10, assume that and are matched except for having different widths, and . Let V, mA/V2, m, m, and . (a) Find the value of R required to establish a current of 90 A in . (b) Find and so that operates at the edge of saturation with a current of 0.9 mA

The transistor in the circuit of Fig. P5.47 has mA/V2, V, and . Show that operation at the edge of saturation is obtained when the following condition is satisfied:

It is required to operate the transistor in the circuit of Fig. P5.47 at the edge of saturation with mA. If V, find the required value of

The PMOS transistor in the circuit of Fig. P5.49 has Vt = 0.6 V, pCox = 100 A/V2, L = 0.25 m, and = 0. Find the values required for W and R in order to establish a drain current of 0.8 mA and a voltage VD of 1.5 V.

The NMOS transistors in the circuit of Fig. P5.50 have Vt = 0.5 V, nCox = 250 A/V2, = 0, and L1 = L2 = 0.25 m. Find the required values of gate width for each of Q1 and Q2, and the value of R, to obtain the voltage and current values indicated.

The NMOS transistors in the circuit of Fig. P5.51 have Vt = 1 V, nCox = 120 A/V2, = 0, and L1 = L2 = L3 = 1m. Find the required values of gate width for each of Q1, Q2, and Q3 to obtain the voltage and current values indicated.

Consider the circuit of Fig. 5.24(a). In Example 5.5 it was found that when Vt = 1 V and (W/L) = 1 mA/V2, the drain current is 0.5 mA and the drain voltage is +7 V. If the transistor is replaced with another having Vt = 2 V and (W/L) = 2 mA/V 2, find the new values of ID and VD. Comment on how tolerant (or intolerant) the circuit is to changes in device parameters.

Using an enhancement-type PMOS transistor with Vt =1.5 V, (W/L) = 1 mA/V2, and = 0, design a circuit that resembles that in Fig. 5.24(a). Using a 10-V supply, design for a gate voltage of +6 V, a drain current of 0.5 mA, and a drain voltage of +5 V. Find the values of RS and RD.

The MOSFET in Fig. P5.54 has Vt = 0.5 V, = 400A/V2, and = 0. Find the required values of W/L and of R so that when vI = VDD = +1.8 V, rDS = 50 , and vO = 50 mV.

In the circuits shown in Fig. P5.55, transistors are characterized by = 2 V, W/L = 1 mA/V2, and = 0. (a) Find the labeled voltages V1 through V7. (b) In each of the circuits, replace the current source with a resistor. Select the resistor value to yield a current as close to that of the current source as possible, while using resistors specified in the 1% table provided in Appendix G. Find the new values of V1 to V7.

For each of the circuits in Fig. P5.56, find the labeled node voltages. For all transistors, (W/L) = 0.5 mA/V2, Vt = 0.8 V, and

For each of the circuits shown in Fig. P5.57, find the labeled node voltages. The NMOS transistors have Vt = 1 V and W/L = 5 mA/V2.

For the PMOS transistor in the circuit shown in Fig. P5.58, W/L = 25, and For I = 100 A, find the voltages VSD and VSG for R = 0, 10 k, 30 k, and 100 k. For what value of R is VSD = VSG? VSD = VSG /2? VSD = VSG/10?

For the circuits in Fig. P5.59, nCox = 2.5 pCox = 20 A/V2, = 0, L = 10 m, and W = 30 m, unless otherwise specified. Find the labeled currents and voltages.

For the devices in the circuits of Fig. P5.60, 1 V, = 0, nCox = 50 A/V2, L = 1 m, and W = 10 m. Find V2 and I2. How do these values change if Q3 and Q4 are made to have W = 100 m?

In the circuit of Fig. P5.61, transistors Q1 and Q2 have Vt = 1 V, and the process transconductance parameter Find V1, V2, and V3 for each of the following cases:

Consider the amplifier of Fig. 5.27(a) with V and with the MOSFET having V, mA/V2 and W/L = 40. (a) Find the value of that will result in the segment AB of the VTC extending over the range to 2.5 V. (b) What are the corresponding values of ? (c) Find which corresponds to . What is the MOSFETs resistance at operating point C? (d) If the amplifier is biased to operate at V, find and the voltage gain.

For the amplifier of Fig. 5.29(a) find an expression for the bias voltage at which the magnitude of voltage gain is at its largest value. What is the value of the gain? What is the maximum allowable signal swing at this bias point? Comment on the practical suitability of this bias point.

Consider the amplifier of Fig. 5.29(a) for the case VDD = 5 V, RD = 24 k, (W/L) = 1 mA/V2, and Vt = 1 V. (a) Find the coordinates of the two end points of the saturation-region segment of the amplifier transfer characteristic, that is, points A and B on the sketch of Fig. 5.29(b). (b) If the amplifier is biased to operate with an overdrive voltage VOV of 0.5 V, find the coordinates of the bias point Q on the transfer characteristic. Also, find the value of ID and of the incremental gain Av at the bias point. (c) For the situation in (b), and disregarding the distortion caused by the MOSFETs square-law characteristic, what is the largest amplitude of a sine-wave voltage signal that can be applied at the input while the transistor remains in saturation? What is the amplitude of the output voltage signal that results? What gain value does the combination of these amplitudes imply? By what percentage is this gain value different from the incremental gain value calculated above? Why is there a difference?

Various measurements are made on an NMOS amplifier for which the drain resistor RD is 20 k. First, dc measurements show the voltage across the drain resistor, VRD, to be 1.5 V and the gate-to-source bias voltage to be 0.7 V. Then, ac measurements with small signals show the voltage gain to be 10 V/V. What is the value of Vt for this transistor? If the process transconductance parameter is 200 A/V2, what is the MOSFETs W/L?

Refer to the expression for the incremental voltage gain in Eq. (5.38). Various design considerations place a lower limit on the value of the overdrive voltage VOV. For our purposes here, let this lower limit be 0.2 V. Also, assume that VDD = 5 V. (a) Without allowing any room for output voltage swing, what is the maximum voltage gain achievable? (b) If we are required to allow for an output voltage swing of 0.5 V, what dc bias voltage should be established at the drain to obtain maximum gain? What gain value is achievable? What input signal results in a 0.5-V output swing? (c) For the situation in (b), find W/L of the transistor to establish a dc drain current of 100 A. For the given process technology, = 100 A/V2. (d) Find the required value of RD.

The expression for the incremental voltage gain Av given in Eq. (5.38) can be written in as where VDS is the bias voltage at the drain. This expression indicates that for given values of VDD and VOV, the gain magnitude can be increased by biasing the transistor at a lower VDS. This, however, reduces the allowable output signal swing in the negative direction. Assuming linear operation around the bias point, show that the largest possible negative output signal peak that is achievable while the transistor remains saturated is = For VDD = 5 V and VOV = 0.5 V, provide a table of values for Av, , and the corresponding for VDS = 1 V, 1.5 V, 2 V, and 2.5 V. If W/L = 1 mA/V2, find ID and RD for the design for which VDS = 1 V.

Figure P5.68 shows an amplifier in which the load resistor RD has been replaced with another NMOS transistor Q2 connected as a two-terminal device. Note that because vDG of Q2 is zero, it will be operating in saturation at all times, even when vI = 0 and iD2 = iD1 = 0. Note also that the two transistors conduct equal drain currents. Using iD1 = iD2, show that for the range of vI over which Q1 is operating in saturation, that is, for the output voltage will be given by where we have assumed Vt1 = Vt2 = Vt. Thus the circuit functions as a linear amplifier, even for large input signals. For = ( m) and = ( m), find the voltage gain.

This problem investigates the nonlinear distortion introduced by a MOSFET amplifier. Let the signal vgs be a sine wave with amplitude Vgs, and substitute vgs = Vgs sin t in Eq. (5.43). Using the trigonometric identity show that the ratio of the signal at frequency 2 to that at frequency , expressed as a percentage (known as the second-harmonic distortion) is If in a particular application Vgs is 10 mV, find the minimum overdrive voltage at which the transistor should be operated so that the second-harmonic distortion is kept to less than 1%.

Consider an NMOS transistor having = 10 mA/V2. Let the transistor be biased at VOV = 0.5 V. For operation in saturation, what dc bias current ID results? If a 0.05-V signal is superimposed on VGS, find the corresponding increment in collector current by evaluating the total collector current iD and subtracting the dc bias current ID. Repeat for a 0.05-V signal. Use these results to estimate gm of the FET at this bias point. Compare with the value of gm obtained using Eq. (5.48).

Consider the FET amplifier of Fig. 5.34 for the case Vt = 0.4 V, = 4 mA/V2, VGS = 0.65 V, VDD = 1.8 V, and RD = 8 k. (a) Find the dc quantities ID and VD. (b) Calculate the value of gm at the bias point. (c) Calculate the value of the voltage gain. (d) If the MOSFET has = 0.1 V1, find ro at the bias point and calculate the voltage gain.

An NMOS amplifier is to be designed to provide a 0.50-V peak output signal across a 50-k load that can be used as a drain resistor. If a gain of at least 5 V/V is needed, Using a dc supply of 1.8 V, what values of ID and VOV would you choose? What W/L ratio is required if

In this problem we investigate an optimum design of the CS amplifier circuit of Fig. 5.34. First, use the voltage gain expression together with Eq. (5.57) for gm to show that Next, let the maximum positive input signal be . To keep the second-harmonic distortion to an acceptable level, we bias the MOSFET to operate at an overdrive voltage VOV  . Let . Now, to maximize the voltage gain we design for the lowest possible VD. Show that the minimum VD that is consistent with allowing a negative signal voltage swing at the drain of while maintaining saturation-mode operation is given by Now, find VOV, VD, Av, and for the case VDD = 2.5 V, = and m = 15. If it is desired to operate this transistor at ID = 100 A, find the values of RD and W/L, assuming that for this process technology

In the table below, for enhancement MOS transistors operating under a variety of conditions, complete as many entries as possible. Although some data is not available, it is always possible to calculate gm using one of Eqs. (5.55), (5.56) or (5.57). Assume n = 500 cm2/Vs, p = 250 cm2/Vs, and Cox = 0.4 fF/m2.

An NMOS technology has nCox = 250 A/V2 and Vt = 0.5 V. For a transistor with L = 0.5 m, find the value of W that results in gm = 1 mA/V at ID = 0.25 mA. Also, find the required VGS.

For the NMOS amplifier in Fig. P5.76, replace the transistor with its T equivalent circuit, assuming . Derive expressions for the voltage gains

In the circuit of Fig. P5.77, the NMOS transistor has = 0.5 V and VA = 50 V and operates with VD = 1 V. What is the voltage gain ? What do VD and the gain become for I increased to 1 mA?

For a 0.8-m CMOS fabrication process: Vtn = 0.8 V, Vtp = 0.9 V, nCox = 90 A/V2, pCox = 30 A/V2, Cox = 1.9 fF/m2, VA (n-channel devices) = 8L (m), and (p-channel devices) = 12L (m). Find the small-signal model parameters (gm and ro) for both an NMOS and a PMOS transistor having W/L = 20 m/2 m and operating at ID = 100 A. Also, find the overdrive voltage at which each device must be operating.

Figure P5.79 shows a discrete-circuit amplifier. The input signal vsig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). (a) If the transistor has Vt = 1 V, and = 2 mA/V2, verify that the bias circuit establishes VGS = 2 V, ID = 1 mA, and VD =+7.5 V. That is, assume these values, and verify that they are consistent with the values of the circuit components and the device parameters. (b) Find gm and ro if VA = 100 V. (c) Draw a complete small-signal equivalent circuit for the amplifier, assuming all capacitors behave as short circuits at signal frequencies. (d) Find

An amplifier with an input resistance of 100 k , an open-circuit voltage gain of 100 V/V and an output resistance of 100 is connected between a 10-k signal source and a 1-k load. Find the overall voltage gain . Also find the current gain, defined as the ratio of the load current to the current drawn from the signal source.

Specify the parameters , and of an amplifier that is to be connected between a 100-k source and a 2-k load and is required to meet the following specifications: (a) No more than 10% of the signal strength is lost in the connection to the amplifier input; (b) If the load resistance changes from the nominal value of 2 k to a low value of 1 k , the change in output voltage is limited to 10% of nominal value; and (c) The nominal overall voltage gain is 10 V/V.

Figure P5.82 shows an alternative equivalent circuit representation of an amplifier. If this circuit is to be equivalent to that in Fig. 5.44(b) show that . Also convince yourself that the transconductance is defined as and hence is known as the short-circuit transconductance. Now, if the amplifier is fed with a signal source and is connected to a load resistance show that the gain is given by and the overall voltage gain is given by

An alternative equivalent circuit of an amplifier fed with a signal source and connected to a load is shown in Fig. P5.83. Here is the open-circuit overall voltage gain, and is the output resistance with set to zero. This is different than . Show that where . Also show that the overall voltage gain is

Most practical amplifiers have internal feedback that make them non-unilateral. In such a case, depends on . To illustrate this point we show in Fig. P5.84 the equivalent circuit of an amplifier where a feedback resistance models the internal feedback mechanism that is present in this amplifier. It is that makes the amplifier non-unilateral. Show that Evaluate , and for the case k , M , mA/V, and k . Which of the amplifier characteristic parameters is most affected by (that is, relative to the case with )?For k determine the overall voltage gain, , with and without present.

Calculate the overall voltage gain of a CS amplifier fed with a 1-M source and connected to a 20-k load. The MOSFET has mA/V and k , and a drain resistance k is utilized.

A CS amplifier utilizes a MOSFET with A/V2, W /L = 10, and V. It is biased at mA and uses k . Find , , and . Also, if a load resistance of 10 k is connected to the output, what overall voltage gain is realized? Now, if a 0.2-V peak sine-wave signal is required at the output, what must the peak amplitude of be?

A common-source amplifier utilizes a MOSFET for which V and is operated at V. What is the value of its ? The amplifier feeds a load resistance k . The designer selects . If it is required to realize an overall voltage gain of V/ V what is needed? Also specify the bias current . If, to increase the output signal swing, is reduced to , what does become?

Two identical CS amplifiers are connected is cascade. The first stage is fed with a source having a resistance k . A load resistance k is connected to the drain of the second stage. Each MOSFET is biased at mA and operates with V. Assume is very large. Each stage utilizes a drain resistance k . (a) Sketch the equivalent circuit of the two-stage amplifier. (b) Calculate the overall voltage gain .

In discrete-circuit amplifiers, is usually much smaller than , and thus can be neglected in determining the voltage gain of the CS amplifier. Nevertheless, it is useful to note that poses an absolute upper limit on the voltage gain of a CS amplifier. Find this upper limit by let ting Express the maximum achievable gain in terms of and .

A MOSFET connected in the CS configuration has a transconductance mA/V. When a resistance is connected in the source lead, the effective transconductance is reduced to 1 mA/V. What do you estimate the value of to be?

A CS amplifier using an NMOS transistor with 4 mA/V is found to have an overall voltage gain of V/V. What value should a resistance inserted in the source lead have to reduce the overall voltage gain to V/V?

The overall voltage gain of a CS amplifier with a resistance k in the source lead was measured and found to be V/V. When is shorted, but the circuit operation remained linear, the gain doubled. What must be? What value of is needed to obtain an overall voltage gain of V/V?

A CG amplifier using an NMOS transistor for which mA/V has a 5-k drain resistance and a 5-k load resistance . The amplifier is driven by a voltage source having a 500 resistance. What is the input resistance of the amplifier? What is the overall voltage gain ? By what factor must the bias current of the MOSFET be changed so that matches ?

A CG amplifier when fed with a signal source having is found to have an overall voltage gain of 10 V/V. When a 200- resistance is added in series with the signal generator the overall voltage gain decreased to 8 V/V. What must of the MOSFET be? If the MOSFET is biased at mA, at what overdrive voltage it must be operating?

A source follower is required to connect a highresistance source to a load whose resistance is nominally 2 k but can be as low as 1 k and as high as 3 k . What is the maximum output resistance that the source follower must have if the output voltage is to remain within % of nominal value? If the MOSFET has mA/V2, at what current must it be biased? At what overdrive voltage is the MOSFET operating? \

Refer to the source-follower equivalent circuit shown in Fig. 5.50(b). Show that Now, with removed, the voltage gain is carefully measured and found to be 0.98. Then, when is connected and its value is varied, it is found that the gain is halved at . If the amplifier remained linear throughout this measurement, what must the values of and be?

A source follower is required to deliver a 0.5-V peak sinusoid to 2-k load. If the peak amplitude of is to be limited to 50 mV, what is the lowest value of at which the MOSFET can be biased? At this bias current, what are the maximum and minimum currents that the MOSFET will be conducting (at the positive and negative peaks of the output sine wave)? What must the peak amplitude of be?

Consider the classical biasing scheme shown in Fig.5.52(c), using a 9-V supply. For the MOSFET, Vt = 1 V, = 0, and . Arrange that the drain current is 1 mA, with about one-third of the supply voltage across each of RS and RD. Use 22 M for the larger of RG1 and RG2. What are the values of RG1, RG2, RS, and RD that you have chosen? Specify them to two significant digits. For your design, how far is the drain voltage from the edge of saturation?

Using the circuit topology displayed in Fig. 5.52(e), arrange to bias the NMOS transistor at ID = 1 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are 5 V. For the NMOS transistor, Vt = 1.0 V, = 0, and . Use a gate-bias resistor of 10 M. Specify RS and RD to two significant digits.

In an electronic instrument using the biasing scheme shown in Fig. 5.52(c), a manufacturing error reduces RS to zero. Let VDD = 12 V, RG1 = 5.6 M, and RG2 = 2.2 M. What is the value of VG created? If supplier specifications allow to vary from 0.2 to 0.3 mA/V2 and Vt to vary from 1.0 V to 1.5 V, what are the extreme values of ID that may result? What value of RS should have been installed to limit the maximum value of ID to 0.5 mA? Choose an appropriate standard 5% resistor value (refer to Appendix G). What extreme values of current now result?

An enhancement NMOS transistor is connected in the bias circuit of Fig. 5.52(c), with VG = 4 V and RS = 2 k. The transistor has Vt = 1 V and = 2 mA/V2. What bias current results? If a transistor for which is 50% higher is used, what is the resulting percentage increase in ID?

The bias circuit of Fig. 5.52(c) is used in a design with VG = 5 V and RS = 2 k. For an enhancement MOSFET with = 2 mA/V2, the source voltage was measured and found to be 2 V. What must Vt be for this device? If a device for which Vt is 0.5 V less is used, what does VS become? What bias current results?

Design the circuit of Fig. 5.52(e) for an enhancement MOSFET having Vt = 1 V and = 2 mA/V2. Let VDD = VSS = 5 V. Design for a dc bias current of 1 mA and for the largest possible voltage gain (and thus the largest possible RD) consistent with allowing a 2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero.

Design the circuit in Fig. P5.104 so that the transistor operates in saturation with VD biased 1 V from the edge of the triode region, with ID = 1 mA and VD = 3 V, for each of the following two devices (use a 10-A current in the voltage divider): (a) and W/L = 0.5 mA/V2 (b) and W/L = 1.25 mA/V2

A very useful way to characterize the stability of the bias current ID is to evaluate the sensitivity of ID relative to a particular transistor parameter whose variability might be large. The sensitivity of ID relative to the MOSFET parameter is defined as and its value, when multiplied by the variability (or tolerance) of K, provides the corresponding expected variability of ID. The purpose of this problem is to investigate the use of the sensitivity function in the design of the bias circuit of Fig. 5.52(e). (a) Show that for Vt constant, (b) For a MOSFET having K = 100 A/V2 with a variability of 10% and Vt = 1 V, find the value of RS that would result in ID = 100 A with a variability of 1%. Also, find VGS and the required value of VSS. (c) If the available supply VSS = 5 V, find the value of RS for ID = 100 A. Evaluate the sensitivity function, and give the expected variability of ID in this case.

For the circuit in Fig. 5.55(a) with I = 0.2 mA, RG = 0, RD = 10 k, and VDD = 2.5 V, consider the behavior in each of the following two cases. In each case, find the voltages VS, VD, and VDS that result. (a) Vt = 1 V and = 1.6 mA/V2 (b) Vt = 0.8 V and = 1.25 mA/V2

In the circuit of Fig. 5.54, let RG = 10 M, RD = 10 k, and VDD = 10 V. For each of the following two transistors, find the voltages VD and VG. (a) Vt = 1 V and = 0.5 mA/V2 (b) Vt = 2 V and = 1.25 mA/V2

Using the feedback bias arrangement shown in Fig. 5.54 with a 5-V supply and an NMOS device for which Vt = 1 V and = 0.6 mA/V2, find RD to establish a drain current of 0.2 mA. If resistor values are limited to those on the 5% resistor scale (see Appendix G), what value would you choose? What values of current and VD result?

Figure P5.109 shows a variation of the feedbackbias circuit of Fig. 5.54. Using a 5-V supply with an NMOS transistor for which Vt = 1 V, = 6.25 mA/V2 and = 0, provide a design that biases the transistor at ID = 2 mA, with VDS large enough to allow saturation operation for a 2-V negative signal swing at the drain. Use 22 M as the largest resistor in the feedback-bias network. What values of RD, RG1, and RG2 have you chosen? Specify all resistors to two significant digits.

Calculate the overall voltage gain Gv of a commonsource amplifier for which gm = 2 mA/V, ro = 50 k, RD = 10 k, and RG = 10 M. The amplifier is fed from a signal source with a Thvenin resistance of 0.5 M, and the amplifier output is coupled to a load resistance of 20 k.

This problem investigates a redesign of the commonsource amplifier of Exercise 5.38 whose bias design was done in Exercise 5.37 and shown in Fig. E5.37. Please refer to these two exercises. (a) The open-circuit voltage gain of the CS amplifier can be written as Verify that this expression yields the results in Exercise 5.38 (i.e., Avo = 15 V/V). (b) Avo can be doubled by reducing VOV by a factor of 2, (i.e., from 1 V to 0.5 V) while VD is kept unchanged. What corresponding values for ID, RD, gm, and ro apply? (c) Find Avo and Ro with ro taken into account. (d) For the same value of signal-generator resistance Rsig = 100 k, the same value of gate-bias resistance RG = 4.8 M, and the same value of load resistance RL = 15 k, evaluate the new value of overall voltage gain Gv with ro taken into account. (e) Compare your results to those obtained in Exercises 5.37 and 5.38, and comment.

The NMOS transistor in the CS amplifier shown in Fig. P5.112 has V and V. (a) Neglecting the Early effect, verify that the MOSFET is operating in saturation with mA and V. What must the MOSFETs be? What is the dc voltage at the drain? (b) Find and . (c) If is a sinusoid with a peak amplitude , find the maximum allowable value of for which the transistor remains in saturation. What is the corresponding amplitude of the output voltage? (d) What is the value of resistance that needs to be inserted in series with capacitor in order to allow us to double the input signal ? What output voltage now results?

The PMOS transistor in the CS amplifier of Fig. P5.113 has V and a very large . (a) Select a value for to bias the transistor at ID = 0.3 mA and V. Assume to have a zero dc component. (b) Select a value for that results in V/V. (c) Find the largest sinusoid that the amplifier can handle while remaining in the saturation region. What is the corresponding signal at the output? (d) If to obtain reasonably linear operation, is limited to 50 mV, what value can be increased to while maintaining saturation-region operation? What is the new value of

Figure P5.114 shows a scheme for coupling and amplifying a high-frequency pulse signal. The circuit utilizes two MOSFETs whose bias details are not shown and a 50- coaxial cable. Transistor Q1 operates as a CS amplifier and Q2 as a CG amplifier. For proper operation, transistor Q2 is required to present a 50- resistance to the cable. This situation is known as proper termination of the cable and ensures that there will be no signal reflection coming back on the cable. When the cable is properly terminated, its input resistance is 50 . What must gm2 be? If Q1 is biased at the same point as Q2, what is the amplitude of the current pulses in the drain of Q1? What is the amplitude of the voltage pulses at the drain of Q1? What value of RD is required to provide 1-V pulses at the drain of Q2?

The MOSFET in the circuit of Fig. P5.115 has Vt = 1 V, = 0.8 mA/V2, and VA = 40 V. (a) Find the values of RS, RD, and RG so that ID = 0.1 mA, the largest possible value for RD is used while a maximum signal swing at the drain of 1 V is possible, and the input resistance at the gate is 10 M. Neglect the Early effect. (b) Find the values of gm and ro at the bias point. (c) If terminal Z is grounded, terminal X is connected to a signal source having a resistance of 1 M, and terminal Y is connected to a load resistance of 40 k, find the voltage gain from signal source to load. (d) If terminal Y is grounded, find the voltage gain from X to Z with Z open-circuited. What is the output resistance of the source follower? (e) If terminal X is grounded and terminal Z is connected to a current source delivering a signal current of 10 A and having a resistance of 100 k, find the voltage signal that can be measured at Y. For simplicity, neglect the effect of ro.

(a) The NMOS transistor in the source-follower circuit of Fig. P5.116(a) has gm = 5 mA/V and a large ro. Find the open-circuit voltage gain and the output resistance. (b) The NMOS transistor in the common-gate amplifier of Fig. P5.116(b) has gm = 5 mA/V and a large ro. Find the input resistance and the voltage gain. (c) If the output of the source follower in (a) is connected to the input of the common-gate amplifier in (b), use the results of (a) and (b) to obtain the overall voltage gain .

In this problem we investigate the large-signal operation of the source follower of Fig. 5.60(a). Specifically, consider the situation when negative input signals are applied. Let the negative signal voltage at the output be V. The current in RL will flow away from ground and will have a value of V/RL. This current will subtract from the bias current I, resulting in a transistor current of (I V/RL). One can use this current value to determine vGS. Now, the signal at the transistor source terminal will be V, superimposed on the dc voltage, which is VGS (corresponding to a drain current of I). We can thus find the signal voltage at the gate vi. For the circuit analyzed in Exercise 5.41, find vi for vo = 1 V, 5 V, 6 V, and 7 V. At each point, find the voltage gain vo/vi and compare to the small-signal value found in Exercise 5.41. What is the largest possible negative-output signal?

In a particular application, an n-channel MOSFET operates with in the range 0 V to 4 V. If is nominally 1.0 V, find the range of that results if and V. If the gate oxide thickness is increased by a factor of 4, what does the threshold voltage become?

A p-channel transistor operates in saturation with its source voltage 3 V lower than its substrate. For V, and V, find

For an NMOS transistor with V, , and V, find If the transistor is biased at mA with V, find and

A depletion-type n-channel MOSFET with mA/V2 and V has its source and gate grounded. Find the region of operation and the drain current for V, 1 V, 3 V, and 5 V. Neglect the channellength-modulation effect.

For a particular depletion-mode NMOS device, V, A/V2, and . When operated at , what is the drain current that flows for V, 2 V, 3 V, and 10 V? What does each of these currents become if the device width is doubled with L the same? With L also doubled?

Neglecting the channel-length-modulation effect show that for the depletion-type NMOS transistor of Fig. P5.123, the relationship is given by , for for (Recall that is negative). Sketch the relationship for the case: V and mA/V2.

The circuits shown in Fig. P5.124 employ negative feedback, a subject we shall study in detail in Chapter 10. Assume that each transistor is sized and biased so that gm = 1 mA/V and ro = 100 k. Otherwise, ignore all dc biasing detail and concentrate on small-signal operation resulting in response to the input signal vsig. For RL = 10 k, R1 = 500 k, and R2 = 1 M, find the overall voltage gain vo/vsig and the input resistance Rin for each circuit. Neglect the body effect. Do these circuits remind you of op-amp circuits? Comment.

For the two circuits in Problem 5.124 (shown in Fig. P5.124), we wish to consider their dc bias design. Since vsig has a zero dc component, we short-circuit its generator. For NMOS transistors with Vt = 0.6 V, find VOV, and VA to bias each device at ID = 0.1 mA and to obtain the values of gm and ro specified in Problem 5.124: namely, gm = 1 mA/V and ro = 100 k. For R1 = 0.5 M, R2 = 1 M, and RL = 10 k, find the required value of VDD.

In the amplifier shown in Fig. P5.126, transistors having Vt = 0.6 V and VA = 20 V are operated at VGS = 0.8 V using the appropriate choice of W/L ratio. In a particular application, Q1 is to be sized to operate at 10 A, while Q2 is intended to operate at 1 mA. For RL = 2 k, the (R1, R2) network sized to consume only 1% of the current in RL, vsig, having zero dc component, and I1 = 10 A, find the values of R1 and R2 that satisfy all the requirements. (Hint: VO must be +2 V.) What is the voltage gain vo/vi? Using a result from a theorem known as Millers theorem (Chapter 9), find the input resistance Rin as Now, calculate the value of the overall voltage gain vo/vsig. Does this result remind you of the inverting configuration of the op amp? Comment. How would you modify the circuit at the input by using an additional resistor and a very large capacitor to raise the gain vo/vsig to 5 V/V? Neglect the body effect.

Consider the bias design of the circuit of Problem 5.126 (shown in Fig. P5.126). For = 200 A/V2 and VDD = 3.3 V, find and to obtain the operating conditions specified in Problem 5.126.