In this problem we investigate the effect of velocity

Sketch the standard CMOS circuit implementation of the SR flip-flop shown in Fig. 15.3.

Sketch the logic-gate implementation of an SR flipflop utilizing two cross-coupled NAND gates. Clearly label the output terminals and the input trigger terminals. Provide the truth table and describe the operation.

For the SR flip-flop of Fig. 15.4, show that if each of the two inverters utilizes matched transistors, that is, then the minimum W/L that each of must have so that switching occurs is Give the sizes of all eight transistors if the flipflop is fabricated in a 0.13-m process for which Use the minimum channel length for all transistors and the minimum size (W/L = 1) for and .

In this problem we investigate the effect of velocity saturation (Section 13.5) on the design of the SR flip-flop in Example 15.1. Specifically, answer part (a) of the question in Example 15.1, taking into account the fact that for this technology, for n-channel devices is 0.6 V and for p-channel devices is 1 V. Assume What is the minimum required value for and for Comment on this value relative to that found in Example 15.1. (Hint: Refer to Eq. 13.100.)

Repeat part (a) of the problem in Example 15.1 for the case of inverters that do not use matched and Rather, assume that each of the inverters uses Find the threshold voltage of each inverter. Then determine the value required for the W/L of each of to so that the flipflop switches.

The CMOS SR flip-flop in Fig. 15.4 is fabricated in a 0.13-m process for which nCox= 4 pCox = 430/V 2, , and The inverters have and (W/L)p = 0.8m/ 0.13 m. The four NMOS transistors in the setreset circuit have equal W/L ratios. (a) Determine the minimum value required for this ratio to ensure that the flip-flop will switch. (b) If a ratio twice the minimum is selected, determine the minimum required width of the set and reset pulses to ensure switching. Assume that the total capacitance between each of the Q and nodes and ground is 20 fF.

Consider another possibility for the circuit in Fig. 15.7: Relabel the R input as and the S input as . Let and normally rest at Let the flip-flop be storing a 0; thus and To set the flip-flop, the terminal is lowered to 0 V and the clock is raised to The relevant part of the circuit is then transistors and For the flip-flop to switch, the voltage at must be lowered to What is the minimum required W/L for in terms of and

The clocked SR flip-flop in Fig. 15.4 is not a fully complementary CMOS circuit. Sketch the fully complementary version by augmenting the circuit with the PUN corresponding to the PDN comprising Q5, Q6, Q7, and Q8. Note that the fully complementary circuit utilizes 12 transistors. Although the circuit is more complex, it switches faster.

Consider the latch of Fig. 15.1 as implemented in CMOS technology. Let nCox = 2 pCox = 20 Wp = 2Wn = 24 m, Lp = Ln = 6 m, and VDD = 5 V. (a) Plot the transfer characteristic of each inverterthat is, vX versus vW, and vZ versus vY. Determine the output of each inverter at input voltages of 1, 1.5, 2, 2.25, 2.5, 2.75, 3, 3.5, 4, and 5 volts. (b) Use the characteristics in (a) to determine the loop voltage-transfer curve of the latchthat is, vZ versus vW. Find the coordinates of points A, B, and C as defined in Fig. 15.1(c). (c) If the finite output resistance of the saturated MOSFET is taken into account, with , find the slope of the loop transfer characteristic at point B. What is the approximate width of the transition region?

Two CMOS inverters operating from a 5-V supply have VIH and VIL of 2.42 and 2.00 V and corresponding outputs of 0.4 V and 4.6 V, respectively, and are connected as a latch. The MOSFETs have Approximating the corresponding transfer characteristic of each gate by straight lines between the break points, sketch the latch open-loop transfer characteristic. What are the coordinates of point B? What is the loop gain at B?

Figure P15.11 shows a commonly used circuit of a D flip-flop that is triggered by the negative-going edge of the clock . (a) For high, what are the values of and Q in terms of D? Which transistors are conducting? (b) If D is high and goes low, which transistors conduct and what signals appear at and at Q? Describe the circuit operation. (c) Repeat (b) for D low with the clock going low. (d) Does the operation of this circuit rely on charge storage?

A particular 1 M-bit square memory array has its peripheral circuits reorganized to allow for the readout of a 16-bit word. How many address bits will the new design need?

For the memory chip described in Problem 15.12, how many word lines must be supplied by the row decoder? How many sense amplifiers/drivers would a straightforward implementation require? If the chip power dissipation is 500 mW with a 5-V supply for continuous operation with a 200-ns cycle time, and all the power loss is dynamic, estimate the total capacitance of all logic activated in any one cycle. If we assume that 90% of this power loss occurs in array access, and that the major capacitance contributor will be the bit line itself, calculate the capacitance per bit line and per bit for this design. (Recall from problem 15.12 that 16 bit lines are selected simultaneously.) If closer manufacturing control allows the memory array to operate at 3 V, how much larger a memory array can be designed in the same technology at about the same power level?

An experimental 1.5-V, 1-Gbit dynamic RAM (called DRAM) by Hitachi uses a 0.16-m process with a cell size of 0.38 0.76 m2 in a 19 38 mm2 chip. What fraction of the chip is occupied by the I/O connections, peripheral circuits, and interconnect?

Consider the read operation of the 6T SRAM cell of Fig. 15.12 when it is storing a 0, that is, and Assume that the bit lines are precharged to before the word-line voltage is raised to Sketch the relevant part of the circuit and describe the operation. Show that the analysis parallels that presented in the text for the read-1 operation.

Consider a 6T SRAM cell fabricated in a 0.18-m CMOS process for which and If during a read-1 operation it is required that does not exceed 0.2 V, use the graph in Fig. 15.14 to determine the maximum allowable value of the ratio For select values for and that minimize the combined areas of and Assume that the minimum width allowed is 0.18 m.

Repeat Exercise 15.4 for an SRAM fabricated in a 0.25-m CMOS process for which and

Repeat Exercise 15.4 for an SRAM fabricated in a 0.13-m CMOS process for which

Locate on the graph of Fig. 15.14 the points A, B, and C that correspond to the following three process technologies: (a) 0.25-m: and (b) 0.18-m: and (c) 0.13-m: and In each case, impose the condition that in a read-1 operation

Refer to the circuit in Fig. 15.13 and find the maximum ratio for this time taking into account the velocity-saturation effect (Section 13.5, Eq. 13.100). The SRAM is fabricated in a 0.18-m CMOS process for which and for the n-channel devices Compare to the value obtained without accounting for velocity saturation. (Hint: Convince yourself that for this situation only will be operating in velocity saturation.)

For the 6T SRAM of Fig. 15.12, fabricated in a 0.18-m CMOS process for which and = 0.3 V1/2, find the maximum ratio for which during a read-1 operation (Fig. 15.13). Take into account the body effect in Compare to the value obtained without accounting for the body effect.

A 6T SRAM cell is fabricated in a 0.13-m CMOS process for which and The inverters utilize (W/L)n = 1. Each of the bit lines has a 2-pF capacitance to ground. The sense amplifier requires a minimum of 0.2-V input for reliable and fast operation.(a) Find the upper bound on for each of the access transistors so that and do not change by more than volts during the read operation. (b) Find the delay time encountered in the read operation if the cell design utilizes minimum-size access transistors. (c) Find the delay time if the design utilizes the maximum allowable size for the access transistors.

Consider the operation of writing a 1 into a 6T SRAM cell that is originally storing a 0. Sketch the relevant part of the circuit and explain the operation. Without doing detailed analysis, show that the analysis would lead to results identical to those obtained in the text for the write-0 operation.

4For a 6T SRAM cell fabricated in a 0.13-m CMOS process, find the maximum permitted value of in terms of of the access transistors. Assume , , and .

For a 6T SRAM cell fabricated in a 0.25-m CMOS process, find the maximum permitted value of in terms of of the access transistors. Assume and

Locate on the graph in Fig. 15.17 the points A, B, and C corresponding to the following three CMOS fabrication processes: (a) 0.25-m: (b) 0.18-m: (c) 0.13-m: For all three, In each case, is to be limited to a maximum value of

Design a minimum-size 6T SRAM cell in a 0.13m process for which and All transistors are to have equal L = 0.13 m. Assume that the minimum width allowed is 0.13 m. Verify that your minimum-size cell meets the constraints in Eqs. (15.5) and (15.11).

For a particular DRAM design, the cell capacitance CS = 30 fF and VDD = 1.8 V. Each cell represents a capacitive load on the bit line of 1 fF. Assume a 28-fF capacitance for the sense amplifier and other circuitry attached to the bit line. What is the maximum number of cells that can be attached to a bit line while ensuring a minimum bit-line signal of 0.05V? How many bits of row addressing can be used? If the sense-amplifier gain is increased by a factor of 5, how many word-line address bits can be accommodated?

For a DRAM available for regular use 98% of the time, having a row-to-column ratio of 2 to 1, a cycle time of 20 ns, and a refresh cycle of 8 ms, estimate the total memory capacity.

In a particular dynamic memory chip, CS = 25 fF, the bit-line capacitance per cell is 0.5 fF, and bit-line control circuitry involves 12 fF. For a 1-Mbit-square array, what bit-line signals result when a stored 1 is read? When a stored 0 is read? Assume that VDD = 1.8 V.

For a DRAM cell utilizing a capacitance of 20 fF, refresh is required within 10 ms. If a signal loss on the capacitor of 0.2 V can be tolerated, what is the largest acceptable leakage current present at the cell?

Consider the operation of the differential sense amplifier of Fig. 15.20 following the rise of the sense control signal s. Assume that a balanced differential signal of 0.1 V is established between the bit lines, each of which has a 1 pF capacitance. For VDD = 3 V, what is the value of Gm of each of the inverters in the amplifier required to cause the outputs to reach 0.1VDD and 0.9VDD [from initial values of 0.5VDD + and 0.5VDD volts, respectively] in 2 ns? If for the matched inverters, = 0.8 V and = 3 = 75A/V2, what are the device widths required? If the input signal is 0.2 V, what does the amplifier response time become?

A particular version of the regenerative sense amplifier of Fig. 15.20 in a 0.5-m technology, uses transistors for which = 0.8 V, = 2.5 = 100 A/V2, VDD = 3.3 V, with ( )n = and ( )p = / . For each inverter, find the value of Gm. For a bit-line capacitance of 0.8 pF, and a delay until an output of 0.9VDD is reached of 2 ns, find the initial difference-voltage required between the two bit lines. If the time can be relaxed by 1 ns, what input signal can be handled? With the increased delay time and with the input signal at the original level, by what percentage can the bit-line capacitance, and correspondingly the bit-line length, be increased? If the delay time required for the bit-line capacitances to charge by the constant current available from the storage cell, and thus develop the difference-voltage signal needed by the sense amplifier, was 5 ns, what does it increase to when longer lines are used?

(a) For the sense amplifier of Fig. 15.20, show that the time required for the bit lines to reach 0.9VDD and 0.1VDD is given by where V is the initial difference-voltage between the two bit lines. (Refer to Fig. 15.21.) (b) If the response time of the sense amplifier is to be reduced to one-half the value of an original design, by what factor must the width of all transistors be increased? (c) If for a particular design, VDD = 1.8 V and V = 0.2 V, find the factor by which the width of all transistors must be increased so that V is reduced by a factor of 4 while keeping td unchanged?

It is required to design a sense amplifier of the type shown in Fig. 15.20 to operate with a DRAM using the dummy-cell technique illustrated in Fig. 15.22. The DRAM cell provides readout voltages of 100 mV when a 0 is stored and +40 mV when a 1 is stored. The sense amplifier is required to provide a differential output voltage of 2 V in at most 5 ns. Find the ratios of the transistors in the amplifier inverters, assuming that the processing technology is characterized by = 2.5 = 100 A/V2, = 1 V, and VDD = 5 V. The capacitance of each half bit line is 1 pF. What will be the amplifier response time when a 0 is read? When a 1 is read?

It is required to design the sense amplifier of Fig. 15.24 to detect an input signal of 100 mV and provide a full output in 0.3 ns. If C = 60 fF and find the required current I and the power dissipation.

Consider the sense amplifier in Fig. 15.24 in the equilibrium condition shown in part (b) of the figure. Let and (a) If and are to operate at the edge of saturation, what is the dc voltage at the drain of (b) If the switching voltage is to be about 140 mV, at what overdrive voltage should and be operated in equilibrium? What dc voltage should appear at the common-source terminals of and (c) If the delay component given by Eq. (15.18) is to be 0.5 ns, what current I is needed if C = 55 fF? (d) Find the W/L required for each of to for (e) If is to operate at the same overdrive voltage as and find its required and the value of the reference voltage

For the column decoder shown in Fig. 15.26, how many column-address bits are needed in a 256-Kbit square array? How many NMOS pass transistors are needed in the multiplexer? How many NMOS transistors are needed in the NOR decoder? How many PMOS transistors? What is the total number of NMOS and PMOS transistors needed?

Consider the use of the tree column decoder shown in Fig. 15.27 for application with a square 256-Kbit array. How many address bits are involved? How many levels of pass gates are used? How many pass transistors are there in total?

Consider a ring oscillator consisting of five inverters, each having ns and ns. Sketch one of the output waveforms, and specify its frequency and the percentage of the cycle during which the output is high.

A ring-of-eleven oscillator is found to operate at 20 MHz. Find the propagation delay of the inverter.

Design the one-shot circuit of Fig. 15.29 to provide an output pulse of 10-ns width. If the inverters available have ns delay, how many inverters do you need for the delay circuit?

Give the eight words stored in the ROM of Fig. 15.30.

Design the bit pattern to be stored in a (16 4) ROM that provides the 4-bit product of two 2-bit variables. Give a circuit implementation of the ROM array using a form similar to that of Fig. 15.30.

Consider a dynamic version of the ROM in Fig. 15.30 in which the gates of the PMOS devices are connected to a precharge control signal . Let all the NMOS devices have = and all the PMOS devices have (a) During the precharge interval, is lowered to 0 V. Estimate the time required to charge a bit line from 0 to 5 V. Use as an average charging current the current supplied by a PMOS transistor at a bit-line voltage halfway through the 0 to 5 V excursion (i.e., 2.5 V). The bit-line capacitance is 1 pF. Note that all NMOS transistors are cut off at this time. (b) After the precharge interval is completed and returns to VDD, the row decoder raises the voltage of the selected word line. Because of the finite resistance and capacitance of the word line, the voltage rises exponentially toward VDD. If the resistance of each of the polysilicon word lines is 5 k and the capacitance between the word line and ground is 2 pF, what is the (10% to 90%) rise time of the word-line voltage? What is the voltage reached at the end of one time-constant? (c) If we approximate the exponential rise of the wordline voltage by a step equal to the voltage reached in one time constant, find the interval t required for an NMOS transistor to discharge the bit line and lower its voltage by 1 V.