For an NMOS transistor fabricated in the 0.18-m process

Find , , , and for the CE amplifier of Fig. 7.1(b) when operated at I = 10 A, 100 A, and 1 mA. Assume and remains constant as I is varied, and that V. Present your results in a table.

Consider the CE amplifiers of Fig. 7.1(b) for the case of I =1 mA, , and V. Find and If it is required to raise by a factor of 4 by changing I, what value of I is required, assuming that remains unchanged? What are the new values of and If the amplifier is fed with a signal source having k and is connected to a load of 100-k resistance, find the overall voltage gain

Find the intrinsic gain of an NMOS transistor fabricated in a process for which A/V2 and Vm. The transistor has a 0.5-m channel length and is operated at V. If a 2-mA/V transconductance is required, what must and W be?

An NMOS transistor fabricated in a certain process is found to have an intrinsic gain of 80 V/V when operated at an of 100 A. Find the intrinsic gain for A and A. For each of these currents, find the factor by which changes from its value at A.

Consider an NMOS transistor fabricated in a 0.18-m technology for which A/V2 and V/m. It is required to obtain an intrinsic gain of 25 V/V and a of 1 mA/V. Using V, find the required values of L, W/L, and the bias current I.

Sketch the circuit for a current-source-loaded CS amplifier that uses a PMOS transistor for the amplifying device. Assume the availability of a single -V dc supply. If the transistor is operated with V, what is the highest instantaneous voltage allowed at the drain?

An NMOS transistor is fabricated in the 0.18-m process whose parameters are given in Table 7.A.1 on page 554. The device has a channel length twice the minimum and is operated at V and A. (a) What values of and are obtained? (b) If is increased to 100 A, what do and become? (c) If the device is redesigned with a new value of W so that it operates at V for A, what do , , and become? (d) If the redesigned device in (c) is operated at 10 A, find and (e) Which designs and operating conditions produce the lowest and highest values of ? What are these values? In each of these two cases, if W/L is held at the same value but L is made 10 times larger, what gains result?

Find for an NMOS transistor fabricated in a CMOS process for which 200 A/V2 and V/m. The transistor has a 0.4-m channel length and is operated with an overdrive voltage of 0.25 V. What must W be for the NMOS transistor to operate at A? Also, find the values of and . Repeat for L = 0.8 m.

Using a CMOS technology for which A/V2 and V/m, design a current-source-loaded CS amplifier for operation at I = 50 A with V. The amplifier is to have an open-circuit voltage gain of V/V. Assume that the current-source load is ideal. Specify L and W/L.

The circuit in Fig.7.3(a) is fabricated in a process for which A/V2, 20V/m, V, and V. The two transistors have L = 0.5 m and are to be operated at A and V. Find the required values of , , and

The circuit in Fig. 7.3(a) is fabricated in a 0.18-m CMOS technology for which A/V2, A/V2, V, V/m, V/m, and V. It is required to design the circuit to obtain a voltage gain V/V. Use devices of equal length L operating at I = 100 A and V. Determine the required values of L, , and

Figure P7.12 shows an IC MOS amplifier formed by cascading two common-source stages. Assuming that and that the biasing current sources have output resistances equal to those of and find an expression for the overall voltage gain in terms of and of and

The NMOS transistor in the circuit of Fig. P7.13 has V, mA/V2, and (a) Neglecting the dc current in the feedback network and the effect of find Then find the dc current in the feedback network and Verify that you were justified in neglecting the current in the feedback network when you found(b) Find the small-signal voltage gain, vo/vi. What is the peak of the largest output sinewave signal that is possible while the NMOS transistor remains in saturation? What is the corresponding input signal? (c) Find the small-signal input resistance

Consider the CMOS amplifier of Fig. 7.4(a) when fabricated with a process for which and Find and to obtain a voltage gain of 40 V/V and an output resistance of 100 k. If Q2 and Q3 are to be operated at the same overdrive voltage as Q1, what must their W/L ratios be?

Consider the CMOS amplifier analyzed in Example 7.3. If consists of a dc bias component on which is superimposed a sinusoidal signal, find the value of the dc component that will result in the maximum possible signal swing at the output with almost-linear operation. What is the amplitude of the output sinusoid resulting? (Note: In practice, the amplifier would have a feedback circuit that causes it to operate at a point near the middle of its linear region.)

The power supply of the CMOS amplifier analyzed in Example 7.3 is increased to 5 V. What will the extent of the linear region at the output become?

Consider the circuit shown in Fig. 7.4(a), using a3.3-V supply and transistors for which and L = 1 m. For Q1, and W = 20m. For Q2 and Q3, and For Q2, W = 40 m. For Q3, W = 10 m. (a) If Q1 is to be biased at 100 A, find For simplicity, ignore the effect of (b) What are the extreme values of for which Q1 and Q2 just remain in saturation? (c) What is the large-signal voltage gain? (d) Find the slope of the transfer characteristic at (e) For operation as a small-signal amplifier around a bias point at find the small-signal voltage gain and output resistance.

The MOSFETs in the circuit of Fig. P7.18 are matched, having and The resistance (a) For G and D open, what are the drain currents and (b) For what is the voltage gain of the amplifier from G to D? [Hint: Replace the transistors with their smallsignal models.] (c) For finite what is the voltage gain from G to D and the input resistance at G? (d) If G is driven (through a large coupling capacitor) from a source having a resistance of 100 k, find the voltage gain (e) For what range of output signals do Q1 and Q2 remain in the saturation region?

Transistor Q1 in the circuit of Fig. P7.19 is operating as a CE amplifier with an active load provided by transistor Q2, which is the output transistor in a current mirror formed by Q2 and Q3. (Note that the biasing arrangement for Q1 is not shown.) (a) Neglecting the finite base currents of Q2 and Q3 and assuming that their and that Q2 has five times the area of Q3, find the value of I. (b) If Q1 and Q2 are specified to have find and and hence the total resistance at the collector of Q1. (c) Find and assuming that (d) Find and

It is required to design the CMOS amplifier of Fig. 7.4(a) utilizing a 0.18-m process for which A/V2, A/V2, V, V, V/m, and V/m. The output voltage must be able to swing to within approximately 0.2 V of the powersupply rails (i.e., from 0.2 V to 1.6 V) and the voltage gain must be at least 10 V/V. Design for a dc bias current of 50 A, and use devices with the same channel length. If the channel length is an integer multiple of the minimum 0.18 m, what channel length is needed and what W/L ratios are required? If it is required to raise the gain by a factor of 2, what channel length would be required, and by what factor does the total gate area of the circuit increase?

In a MOS cascode amplifier, the cascode transistor is required to raise the output resistance by a factor of 40. If the transistor is operated at V, what must its be? If the process technology specifies as 5 V/m, what channel length must the transistor have?

For a cascode current source such as that in Fig. 7.10, show that if the two transistors are identical, the current I supplied by the current source and the output resistance are related by . Now consider the case of transistors that have V and are operated at of 0.2 V. Also, let A/V2. Find the W/L ratios required and the output resistance realized for the two cases: (a) I = 0.1 mA and (b) I = 0.5 mA. Assume that for the two devices is the minimum required (i.e., ).

For a cascode current source, such as that in Fig. 7.10, show that if the two transistors are identical, the current I supplied by the current source and the output resistance are related by Now consider the case of a 0.18-m technology for which V/m and let the transistors be operated at V. Find the figure-of-merit for the three cases of L equal to the minimum channel length, twice the minimum, and three times the minimum. Complete the entries of the table at the bottom of the page. Give W/L and the area 2WL in terms of n. In the table, Av denotes the gain obtained in a cascode amplifier such as that in Fig. 7.11 that utilizes our current source as load and which has the same values of gm and Ro as the current-source transistors. (a) For each current value, what is price paid for the increase in and obtained as L is increased? (b) For each value of L, what advantage is obtained as I is increased, and what is the price paid? (c) Contrast the performance obtained from the circuit with the largest area with that obtained from the circuit with the smallest area.

Design the cascode amplifier of Fig. 7.9(a) to obtain mA/V and k . Use a 0.18-m technology for which V, V/m and A/V2. Determine L, W/L, , and I. Use identical transistors operated at V, and design for the maximum possible negative signal swing at the output. What is the value of the minimum permitted output voltage?

The cascode amplifier of Fig. 7.11 is operated at a current of 0.1 mA with all devices operating at All devices have V. Find the output resistance of the amplifier, the output resistance of the current source, the overall output resistance, and the voltage gain,

Design the CMOS cascode amplifier in Fig. 7.11 for the following specifications: mA/V and V/V. Assume that for the available fabrication process, V/m for both NMOS and PMOS devices and that A/V2. Use the same channel length L for all devices and operate all four devices at V. Determine the required channel length L, the bias current I, and the W/L ratio for each of four transistors. Assume that suitable bias voltages have been chosen, and neglect the Early effect in determining the W/L ratios.

Design the circuit of Fig. 7.10 to provide an output current of 100 A. Use and assume the PMOS transistors to have and The current source is to have the widest possible signal swing at its output. Design for and specify the values of the transistor W/L ratios and of VG3 and VG4. What is the highest allowable voltage at the output? What is the value of Ro?

The cascode transistor can be thought of as providing a shield for the input transistor from the voltage variations at the output. To quantify this shielding property of the cascode, consider the situation in Fig. P7.28. Here we have grounded the input terminal (i.e., reduced vi to zero), applied a small change vx to the output node, and denoted the voltage change that results at the drain of Q1 by vy . By what factor is vy smaller thanvx?

In this problem we investigate whether, as an alternative to cascoding, we can simply increase the channel length L of the CS MOSFET. Specifically, we wish to compare the two circuits shown in Fig. P7.29(b) and (c). The circuit in Fig. P7.29(b) is a CS amplifier in which the channel length has been quadrupled relative to that of the original CS amplifier inFig. P7.29(a) while the drain bias current has been keptconstant.(a) Show that for this circuit is double that of the original circuit, gm is half that of the original circuit, and A0 is double that of the original circuit. (b) Compare these values to those of the cascode circuit in Fig. P7.29(c), which is operating at the same bias current and has the same minimum voltage requirement at the drain as in the circuit of Fig. P7.29(b).

Consider the cascode amplifier of Fig. 7.11 with the dc component at the input V, V, V, V, and V. If all devices are matched, that is , and have equal of 0.5 V, what is the overdrive voltage at which the four transistors are operating? What is the allowable voltage range at the output?

Figure P7.31 shows a CG transistor fed with a signal source (vsig, Rsig) and loaded with a resistance (a) Find (b) Noting that the current through is equal to the input current i, find an expression for the overall voltage gain . (c) Determine the values of and for the case of k and k

The CG transistor in Fig. P7.31 can be replaced by an equivalent circuit consisting of a controlled-source and an output resistance as shown in Fig. P7.32. Here is the short-circuit transconductance. Its value can be determined by short-circuiting d to ground, finding the value of i, and dividing it by The value of is that of a CG transistor with a resistance in its source (Refer to Fig. 7.13). (a) Find expressions for and (b) For the case k , and k find and

A CMOS cascode amplifier has identical CS and CG transistors that have W/L = 5.4 m/0.36 m and biased at I = 0.2 mA. The fabrication process has , A/V2, and = 5 V/m. At what value of does the gain become 100 V/V? What is the voltage gain of the common-source stage?

The purpose of this problem is to investigate the signal currents and voltages at various points throughout a cascode amplifier circuit. Knowledge of this signal distribution is very useful in designing the circuit so as to allow for the required signal swings. Figure P7.34 shows a CMOS cascode amplifier with all dc voltages replaced with signal grounds. As well, we have explicitly shown the resistance of each of the four transistors. For simplicity, we are assuming that the four transistors have the same and The amplifier is fed with a signal (a) Determine R1, R2, and R3. (b) Determine , , and all in terms of . (c) Determine v1, v2, and v3, all in terms of vi. (d) If is a 5-mV peak sine wave and , sketch and clearly label the waveforms of , and .

Figure P7.35 shows a CS amplifier with a resistance in the source lead and with the drain short-circuited to ground. Determine the short-circuit transconductance Hence provide the output equivalent circuit of the source-degenerated CS amplifier, and show that the open-circuit voltage gain

A CS amplifier operating with a of 2 mA/V and having k has a 2-k resistance connected in its source lead. Find the output resistance Recalling that the open-circuit voltage gain remains unchanged at find the gain obtained with

Design the double-cascode current source shown in Fig. P7.37 to provide I = 0.1 mA and the largest possible signal swing at the output; that is, design for the minimum allowable voltage across each transistor. The 0.18-m CMOS fabrication process available has V, V/m, and A/V2. Use devices with L = 0.5 m, and operate at V. Specify , and the W/L ratios of the transistors. What is the value of achieved?

Figure P7.38 shows a folded-cascode CMOS amplifier utilizing a simple current source supplying a current 2I, and a cascoded current-source ( ) supplying a current I. Assume, for simplicity, that all transistors have equal parameters and (a) Give approximate expressions for all the resistances indicated. (b) Find the amplifier output resistance (c) Show that the short-circuit transconductance is approximately equal to (d) Find the overall voltage gain and evaluate its value for the case mA/V and

A cascode current source formed of two pnp transistors for which and V supplies a current of 0.5 mA. What is the output resistance?

Use Eq. (7.45) to show that for a BJT cascode current source utilizing identical pnp transistors and supplying a current I, Rs Evaluate the figure-of-merit for the case V and Now find for the cases of I = 0.1, 0.5, and 1.0mA.

Consider the BJT cascode amplifier of Fig. 7.19 for the case all transistors have equal and Show that the voltage gain can be expressed in the form Evaluate for the case V and Note that except for the fact that depends on I as a second-order effect, the gain is independent of the bias current I!

A bipolar cascode amplifier has a current-source load with an output resistance Let , V, and I = 0.1 mA. Find the voltage gain

Find the value of the resistance which, when connected in the emitter lead of a CE BJT amplifier, raises the output resistance by a factor of (a) 5, (b) 10, and (c) 50. What is the maximum possible factor by which the output resistance can be raised, and at what value of is it achieved? Assume the BJT has and is biased at mA.

Consider the CE amplifier with an emitterdegeneration resistance shown in Fig. P7.44(a). It is required to represent the output circuit of the amplifier with the equivalent circuit shown in Fig. P7.44(b). Here is the open-circuit voltage gain and is the output resistance (given by Eq. 7.50). Replace the BJT with its hybrid model, set (i.e., open-circuit the collector), and show that Now, use this result to find the overall short-circuit transconductance (see Fig. P7.44c) and show that State clearly all the approximations you made to arrive at this expression for For a BJT with and k biased at mA and having a resistance in its emitter, find and Also calculate the voltage gain obtained with k

Figure P7.45 shows four possible realizations of the folded cascode amplifier. Assume that the BJTs have and that both the BJTs and the MOSFETs have V. Let I = 100 A, and assume that the MOSFETs are operating at V. Assume the current sources are ideal. For each circuit determine, and Comment on your results.

For and using it is required to design the circuit of Fig. 7.22 to obtain an output current whose nominal value is 100 A. Find R if Q1 and Q2 are matched with channel lengths of 0.5 m, channel widths of 4 m, and What is the lowest possible value of VO? Assuming that for this process technology the Early voltage V/m, find the output resistance of the current source. Also, find the change in output current resulting from a +0.5-V change in VO.

Using and a pair of matched MOSFETs, design the current-source circuit of Fig. 7.22 to provide an output current of 200-A nominal value. To simplify matters, assume that the nominal value of the output current is obtained at . It is further required that the circuit operate for VO in the range of 0.2 V to VDD and that the change in IO over this range be limited to 5% of the nominal value of IO. Find the required value of R and the device dimensions. For the fabrication-process technology utilized, A/V2, V/m, and

Sketch the p-channel counterpart of the current-source circuit of Fig. 7.22. Note that while the circuit of Fig. 7.22 should more appropriately be called a current sink, the corresponding PMOS circuit is a current source. Let Q1 and Q2 be matched, and A/V2. Find the device W/L ratios and the value of the resistor that sets the value of so that a nominally 80-A output current is obtained. The current source is required to operate for VO as high as 1.6 V. Neglect channel-length modulation.

Consider the current-mirror circuit of Fig. 7.23 with two transistors having equal channel lengths but with Q2 having a width five times that of Q1. If is 20 A and the transistors are operating at an overdrive voltage of 0.2 V, what IO results? What is the minimum allowable value of VO for proper operation of the current source? If V, at what value of VO will the nominal value of IO be obtained? If VO increases by 1 V, what is the corresponding increase in IO? Let V.

For the current-steering circuit of Fig. P7.50, find IO in terms of and device W/L ratios.

The current-steering circuit of Fig. P7.51 is fabricated in a CMOS technology for which 10V/ m, and If all devices have L = 0.8 m, design the circuit so that and Use the minimum possible device widths needed to achieve proper operation of the current source Q2 for voltages at its drain as high as +1.3 V and proper operation of the current sink Q5 with voltages at its drain as low as 1.3 V. Specify the widths of all devices and the value of R. Find the output resistance of the current source Q2 and the output resistance of the current sink

A PMOS current mirror consists of three PMOS transistors, one diode connected and two used as current outputs. All transistors have A/V2, and L= 1.0 m but three different widths, namely, 10 m, 20 m, and 40 m. When the diode-connected transistor is supplied from a 100-A source, how many different output currents are available? Repeat with two of the transistors diode connected and the third used to provide current output. For each possible input-diode combination, give the values of the output currents and of the that results.

Although thus far we have focused only on their application in dc biasing, current mirrors can also be used as signalcurrent amplifiers. One such application is illustrated in Fig. P7.53. Here Q1 is a common-source amplifier fed with , where is the gate-to-source dc bias voltage of Q1 and is a small signal to be amplified. Find the signal component of the output voltage and hence the small-signal voltage gain . For this purpose, you may neglect all ros. Also, find the small-signal resistance of the diode-connected transistor Q2 in terms of gm2 and ro2, and hence the total resistance between the drain of Q1 and ground. What is the voltage gain of the CS amplifier Q1?

Consider the basic bipolar current mirror of Fig. 7.28 for the case in which Q1 and Q2 are identical devices having (a) Assuming the transistor is very high, find the range of and IO corresponding to increasing from 10 A to 10 mA. Assume that Q2 remains in the active mode, and neglect the Early effect. (b) Find the range of IO corresponding to in the range of 10 A to 10 mA, taking into account the finite . Assume that remains constant at 100 over the current range 0.1 mA to 5 mA but that at  10 A and at Specify IO corresponding to 0.1 mA, 1 mA, and 10 mA. Note that variation with current causes the current transfer ratio to vary with current.

Consider the basic BJT current mirror of Fig. 7.28 for the case in which Q2 has m times the area of Q1. Show that the current transfer ratio is given by Eq. (7.69). If is specified to be a minimum of 50, what is the largest current transfer ratio possible if the error introduced by the finite is limited to 10%?

Give the circuit for the pnp version of the basic current mirror of Fig. 7.28. If of the pnp transistor is 20, what is the current gain (or transfer ratio) for the case of identical transistors, neglecting the Early effect?

Consider the basic BJT current mirror of Fig. 7.28 when Q1 and Q2 are matched and Neglecting the effect of finite , find the change in IO, both as an absolute value and as a percentage, corresponding to VO changing from 1 V to 10 V. The Early voltage is 90 V.

The current-source circuit of Fig. P7.58 utilizes a pair of matched pnp transistors having , and V. It is required to design the circuit to provide an output current mA at VO = 2 V. What values of and R are needed? What is the maximum allowed value of VO while the current source continues to operate properly? What change occurs in IO corresponding to VO changing from the maximum positive value to 5 V?

Find the voltages at all nodes and the currents through all branches in the circuit of Fig. P7.59. Assume V and

For the circuit in Fig. P7.60, let and Find I, V1, V2, V3, V4, and V5 for (a)

Using the ideas embodied in Fig. 7.31, design a multiple-mirror circuit using power supplies of 5 V to create source currents of 0.2 mA, 0.4 mA, and 0.8 mA and sink currents of 0.5 mA, 1 mA, and 2 mA. Assume that the BJTs have and large . What is the total power dissipated in your circuit?

Figure P7.62 shows a current-mirror circuit prepared for small-signal analysis. Replace the BJTs with their hybridmodels and find expressions for and where is the output short-circuit current. Assume

For the constant-current source circuit shown in Fig. P7.63, find the collector current I and the output resistance. The BJT is specified to have = 100 and If the collector voltage undergoes a change of 10 V while the BJT remains in the active mode, what is the corresponding change in collector current?

For the MOS cascode current mirror of Fig. 7.32 with V, mA/V2, V, and 100A, find and the minimum allowable voltage at the output. At what value of is equal to What does become at V?

In a particular cascoded current mirror, such as that shown in Fig. 7.32, all transistors have L = 1 m, and Width 4m, and The reference current IREF is 20 A. What output current results? What are the voltages at the gates of Q2 and Q3? What is the lowest voltage at the output for which current-source operation is possible? What are the values of gm and ro of Q2 and Q3? What is the output resistance of the mirror?

Find the output resistance of the double-cascode current mirror of Fig. P7.66.

For the base-current-compensated mirror of Fig. 7.33, let the three transistors be matched and specified to have a collector current of 1 mA at For IREF of 100 A and assuming = 200, what will the voltage at node x be? If IREF is increased to 1 mA, what is the change in Vx? What is the value of IO obtained with in both cases? Give the percentage difference between the actual and ideal value of IO. What is the lowest voltage at the output for which proper current-source operation is maintained?

Extend the current-mirror circuit of Fig. 7.33 to n outputs. What is the resulting current transfer ratio from the input to each output, IO/IREF? If the deviation from unity is to be kept at 0.1% or less, what is the maximum possible number of outputs for BJTs with

For the base-current-compensated mirror of Fig. 7.33, show that the incremental input resistance (seen by the reference current source) is approximately 2 VT/IREF. Evaluate Rin for IREF = 100 A. [Hint: Q3 is operating at a current IE3 =2 IC/ , where IC is the operating current of each of Q1 and Q2. Replace each transistor with its T model and neglect r0.]

Consider the Wilson current-mirror circuit of Fig. 7.34 when supplied with a reference current IREF of 1 mA. What is the change in IO corresponding to a change of +10 V in the voltage at the collector of Q3? Give both the absolute value and the percentage change. Let = 100 and VA = 100 V.

(a) The circuit in Fig. P7.71 is a modified version of the Wilson current mirror. Here the output transistor is split into two matched transistors, Q3 and Q4. Find IO1 and IO2 in terms of IREF. Assume all transistors to be matched with current gain . (b) Use this idea to design a circuit that generates currents of 0.1 mA, 0.2 mA, and 0.4 mA, using a reference current source of 0.7 mA. What are the actual values of the currents generated for

Use the pnp version of the Wilson current mirror to design a 0.2-mA current source. The current source is required to operate with the voltage at its output terminal as low as 2.5 V. If the power supplies available are 2.5 V, what is the highest voltage possible at the output terminal?

For the Wilson current mirror of Fig. 7.34, show that the incremental input resistance seen by IREF is approximately 2VT /IREF. (Neglect the Early effect in this derivation.) Evaluate Rin for IREF = 100 A.

Consider the Wilson MOS mirror of Fig. 7.35(a) for the case of all transistors identical, with W/L = 12.5, A/V2, and V. The mirror is fed with A. (a) Obtain an estimate of and at which the three transistors are operating, by neglecting the Early effect. (b) Noting that and are operating at different obtain an approximate value for the difference in their currents and hence determine (c) To eliminate the systematic error between and caused by the difference in between and a diode-connected transistor can be added to the circuit as shown in Fig. 7.35(c). What do you estimate now to be? (d) What is the minimum allowable voltage at the output node of the mirror? (e) Convince yourself that will have no effect on the output resistance of the mirror. Find (f) What is the change in (both absolute value and percentage) that results from V?

Show that the input resistance (seen by ) for the Wilson MOS mirror of Fig. 7.35(a) is given by . Assume that all three transistors are identical and neglect the Early effect. [Hint: Replace all transistors by their T model and remember that is equivalent to a resistance

(a) Utilizing a reference current of 100 A, design a Widlar current source to provide an output current of 10 A. Let the BJTs have vBE = 0.8 V at 1-mA current, and assume to be high. (b) If =200 and VA = 50 V, find the value of the output resistance, and find the change in output current corresponding to a 5-V change in output voltage.

Design three Widlar current sources, each having a 100-A reference current: one with a current transfer ratio of 0.9, one with a ratio of 0.10, and one with a ratio of 0.01, all assuming high . For each, find the output resistance, and contrast it with ro of the basic unity-ratio source for which RE =0. Use

The BJT in the circuit of Fig. P7.78 has VBE = 0.7 V, = 100, and VA = 50 V. Find Ro

(a) For the circuit in Fig. P7.79, assume BJTs with high and vBE = 0.8 V at 1 mA. Find the value of R that will result in IO = 10 A. (b) For the design in (a), find Ro assuming = 100 and VA = 50 V.

If the pnp transistor in the circuit of Fig. P7.80 is characterized by its exponential relationship with a scale current IS, show that the dc current I is determined by IR = VT ln(I/IS). Assume Q1 and Q2 to be matched and Q3, Q4, and Q5 to be matched. Find the value of R that yields a current I = 100 A. For the BJT, VEB = 0.7 V at IE = 1 mA.

The transistors in the circuit of Fig. P7.81 have and V. (a) Find and the overall voltage gain. (b) What is the effect of increasing the bias currents by a factor of 10 on and the power dissipation?

Consider the BiCMOS amplifier shown in Fig. P7.82. The BJT has V and . The MOSFET has V and mA/V2. Neglect the Early effect in both devices. (a) Consider the dc bias circuit. Neglect the base current in in determining the current in Find the dc bias currents in and and show that they are approximately 100 A and 1 mA, respectively. (b) Evaluate the small-signal parameters of and at their bias points. (c) Determine the voltage gain For this purpose you can neglect (d) Noting that is connected between the input node where the voltage is and the output node where the voltage is , find and hence the overall voltage gain (e) To considerably reduce the effect of on and hence on consider the effect of adding another resistor in series with the existing one and placing a large bypass capacitor between their joint node and ground. What will and become?

The BJTs in the Darlington follower of Fig. P7.83 have = 100. If the follower is fed with a source having a 100-k resistance and is loaded with 1 k, find the input resistance and the output resistance (excluding the load). Also find the overall voltage gain, both open-circuited and with load.

For the amplifier in Fig. 7.41(a), let I = 1 mA and = 120, and neglect ro. Assume that a load resistance of 10 k is connected to the output terminal. If the amplifier is fed with a signal vsig having a source resistance find Gv.

Consider the CDCG amplifier of Fig. 7.41(c) for the case gm = 5 mA/V, and Rsig = RL = 20 k. Neglecting ro, find Gv.

In each of the six circuits in Fig. P7.86, let = 100, and neglect ro. Calculate the overall voltage gain.

In each of the six circuits in Fig. P7.86, let = 100, and neglect ro. Calculate the overall voltage gain.

What range of IC is obtained in an npn transistor as a result of changing the area of the emitterbase junction by a factor of 10 while keeping VBE constant? If IC is to be kept constant, by what amount must VBE change?

For each of the CMOS technologies specified in Table 7.A.1, find the and hence the required to operate a device with a W/L of 10 at a drain current ID = 100 A. Ignore channel-length modulation.

Consider NMOS and PMOS devices fabricated in the 0.25-m process specified in Table 7.A.1. If both devices are to operate at and ID = 100 A, what must their W/L ratios be?

Consider NMOS and PMOS transistors fabricated in the 0.25-m process specified in Table 7.A.1. If the two devices are to be operated at equal drain currents, what must the ratio of (W/L)p to (W/L)n be to achieve equal values of gm?

An NMOS transistor fabricated in the 0.18-m CMOS process specified in Table 7.A.1 is operated at Find the required W/L and ID to obtain a gm of 10 mA/V. At what value of IC must an npn transistor be operated to achieve this value of gm?

For each of the CMOS process technologies specified in Table 7.A.1, find the gm of an NMOS and a PMOS transistor with W/L = 10 operated at ID = 100 A.

An NMOS transistor operated with an overdrive voltage of 0.25 V is required to have a gm equal to that of an npn transistor operated at IC = 0.1 mA. What must ID be? What value of gm is realized?

It is required to find the incremental (i.e., small-signal) resistance of each of the diode-connected transistors shown in Fig. P7.95. Assume that the dc bias current I = 0.1 mA. For the MOSFET, let A/V2 and W/L = 10.

For an NMOS transistor with L = 1 m fabricated in the 0.8-m process specified in Table 7.A.1, find gm, and if the device is operated with and ID = 100 A. Also, find the required device width W.

For an NMOS transistor with L = 0.3 m fabricated in the 0.18-m process specified in Table 7.A.1, find gm, and obtained when the device is operated at ID = 100 A with Also, find

Fill in the table below. For the BJT, let = 100 and VA = 100 V. For the MOSFET, let W/L = 40, and VA = 10 V. Note that Rin refers to the input resistance at the control input terminal (gate, base) with the (source, emitter) grounded.

For an NMOS transistor fabricated in the 0.18-m process specified in Table 7.A.1 with L = 0.3 m and W = 6 m, find the value of fT obtained when the transistor is operated at Use both the formula in terms of and and the approximate formula. Why does the approximate formula overestimate fT?

An NMOS transistor fabricated in the 0.18-m process specified in Table 7.A.1 and having L = 0.3 m and W = 6 m is operated at and used to drive a capacitive load of 100 fF. Find , (or ), and . At what ID value is the transistor operating? If it is required to double , what must ID become? What happens to and in this case?

For an npn transistor fabricated in the high-voltage process specified in Table 7.A.2, evaluate at 100 A, and 1 mA. Assume . Repeat for the lowvoltage process.

Consider an NMOS transistor fabricated in the 0.8-m process specified in Table 7.A.1. Let the transistor have L = 1m, and assume it is operated at (a) For find W, and fT. (b) To what must be changed to double fT? Find the new values of W, and

For a lateral pnp transistor fabricated in the highvoltage process specified in Table 7.A.2, find fT if the device is operated at a collector bias current of 1 mA. Compare to the value obtained for a vertical npn.

Show that for a MOSFET the selection of L and determines and fT. In other words, show that and fT will not depend on ID and W.

Consider an NMOS transistor fabricated in the 0.18m technology specified in Table 7.A.1. Let the transistor be operated at Find and fT for L = 0.2 m, 0.3m, and 0.4 m.

Consider an NMOS transistor fabricated in the 0.5m process specified in Table 7.A.1. Let L = 0.5 m and 0.3 V. If the MOSFET is connected as a common-source amplifier with a load capacitance (as in Fig. 7.A.2a), find the required transistor width W and bias current ID to obtain a unity-gain bandwidth of 100 MHz. Also, find and .

The circuit shown in Fig.P7.107 is known as a current conveyor (a) Assuming that Y is connected to a voltage V, a current I is forced into X, and terminal Z is connected to a voltage that keeps Q5 in the active region, show that a current equal to I flows through terminal Y, that a voltage equal to V appears at terminal X, and that a current equal to I flows through terminal Z. Assume to be large. Corresponding transistors are matched, and all transistors are operating in the active region. (b) With Y connected to ground, show that a virtual ground appears at X. Now, if X is connected to a +5-V supply through a 10-k resistor, what current flows through Z?

For the PMOS differential amplifier shown in Fig. P8.2 let Vtp = 0.8 V and = 4 mA/V2. Neglect channel-length modulation. (a) For vG1 = vG2 = 0 V, find VOV and VGS for each of Q1 and Q2. Also find VS, VD1, and VD2. (b) If the current source requires a minimum voltage of 0.5 V, find the input common-mode range.

For the differential amplifier specified in Problem 8.1 let vG2 = 0 and vG1 = vid. Find the value of vid that corresponds to each of the following situations: (a) iD1 = iD2 = 0.1 mA; (b) iD1 = 0.15 mA and iD2 = 0.05 mA; (c) iD1 = 0.2 mA and iD2 = 0 (Q2 just cuts off); (d) iD1 = 0.05 mA and iD2 = 0.15 mA; (e) iD1 = 0 mA (Q1 just cuts off) and iD2 = 0.2 mA. For each case, find vS, vD1, vD2, and (vD2 vD1).

For the differential amplifier specified in Problem 8.2, let vG2 = 0 and vG1 = vid. Find the range of vid needed to steer the bias current from one side of the pair to the other. At each end of this range, give the value of the voltage at the common-source terminal and the drain voltages.

Consider the differential amplifier specified in Problem 8.1 with G2 grounded and vG1 = vid. Let vid be adjusted to the value that causes iD1 = 0.11 mA and iD2 = 0.09 mA. Find the corresponding values of vGS2, vS, vGS1, and hence vid. What is the difference output voltage vD2vD1? What is the voltage gain (vD2 vD1)vid? What value of vid results in iD1 = 0.09 mA and iD2 = 0.11 mA?

Design the circuit in Fig. P8.6 to obtain a dc voltage of +0.2V at each of the drains of and when V. Operate all transistors at V and assume that for the process technology in which the circuit is fabricated, V and A/V2. Neglect channel-length modulation. Determine the values of R, and the W/L ratios of , and What is the input common-mode voltage range for your design?

The table providing the answers to Exercise 8.3 shows that as the maximum input signal to be applied to the differential pair is increased, linearity is maintained at the same level by operating at a higher VOV. If |vid|max is to be 160 mV, use the data in the table to determine the required VOV and the corresponding values of W / L and gm.

Use Eq. (8.23) to show that if the term involving is to be kept to a maximum value of k then the maximum possible fractional change in the transistor current is given by and the corresponding maximum value of vid is given by Evaluate both expressions for k = 0.01, 0.1, and 0.2.

An NMOS differential amplifier utilizes a bias current of 400 A. The devices have Vt = 0.5 V, W = 20 m, and L = 0.5 m, in a technology for which nCox = 200 A/V2. Find VGS, and gm in the equilibrium state. Also find the value of vid for full-current switching. To what value should the bias current be changed in order to double the value of vid for full-current switching?

Design the MOS differential amplifier of Fig. 8.5 to operate at VOV = 0.25 V and to provide a transconductance gm of 1 mA/V. Specify the W / L ratios and the bias current. The technology available provides Vt = 0.8 V and nCox = 100 A/V2.

Consider the NMOS differential pair illustrated in Fig. 8.5 under the conditions that I = 100 A, using FETs for which and Vt = 1 V. What is the voltage on the common-source connection for vG1 = vG2 = 0? 2 V? What is the relation between the drain currents in each of these situations? Now for vG2 = 0 V, at what voltages must vG1 be placed to reduce iD2 by 10%? to increase iD2 by 10%? What is the differential voltage, vid = vG2 vG1, for which the ratio of drain currents iD2iD1 is 1.0? 0.5? 0.9? 0.99? For the current ratio iD1iD2 = 20.0, what differential input is required?

(a) For the MOS differential amplifier of Fig. 8.1 with and use Eqns. (8.23) and (8.24) to derive an expression for the output differential voltage in terms of the input differential voltage (b) Sketch and clearly label the voltage transfer characteristic (VTC), that is, versus , over the range , where is the overdrive voltage at which each transistor is operating in the equilibrium state. What is the slope of the nearly linear portion of the VTC near the origin? This is the differential voltage gain. (c) Show on the same coordinates how the VTC changes if the bias current I is doubled? What is the change in the differential voltage gain? (d) Prepare another sketch for case (b). Show on the same coordinates what happens to the VTC if the W/L ratio of each transistor is doubled. What is the change in the differential voltage gain?

An NMOS differential amplifier is operated at a bias current I of 0.4 mA and has a W / L ratio of 32, nCox = 200 A/V2, VA = 10 V, and RD = 5 k. Find VOV, gm, ro, and Ad.

It is required to design an NMOS differential amplifier to operate with a differential input voltage that can be as high as 0.1 V while keeping the nonlinear term under the square root in Eq. (8.23) to a maximum of 0.05. A transconductance gm of 1 mA/V is needed. Find the required values of VOV, I, and W / L. Assume that the technology available has nCox = 200 A/V2. What differential gain Ad results when RD = 10 k? Assume = 0. What is the resulting output signal corresponding to vid at its maximum value?

Design a MOS differential amplifier to operate from -V power supplies and dissipate no more than 2 mW in the equilibrium state. The differential voltage gain is to be 5 V/V and the output common-mode dc voltage is to be 0.5 V. (Note: This is the dc voltage at the drains). Assume A/V2 and neglect the Early effect. Specify I, and W/L.

Design a MOS differential amplifier to operate from supplies and dissipate no more than 2 mW in its equilibrium state. Select the value of so that the value of that steers the current from one side of the pair to the other is 0.4 V. The differential voltage gain is to be 5 V/V. Assume A/V2 and neglect the Early effect. Specify the required values of I, and W/L.

An NMOS differential amplifier employing equal drain resistors, k , has a differential gain of 20 V/V. (a) What is the value of for each of the two transistors? (b) If each of the two transistors is operating at an overdrive voltage V, what must the value of I be? (c) For what is the dc voltage across each (d) If is 20-mV peak-to-peak sine wave applied in a balanced manner but superimposed on V, what is the lowest value that must have to ensure saturationmode operation for and at all times? Assume V.

A MOS differential amplifier is designed to have a differential gain equal to the voltage gain obtained from a common-source amplifier. Both amplifiers utilize the same values of and supply voltages, and all the transistors have the same W/L ratios. What must the bias current I of the differential pair be relative to the bias current of the CS amplifier? What is the ratio of the power dissipation of the two circuits?

A differential amplifier is designed to have a differential voltage gain equal to the voltage gain of a commonsource amplifier. Both amplifiers use the same values of and supply voltages and are designed to dissipate equal amounts of power in their equilibrium or quiescent state. As well, all the transistors use the same channel length. What must the width W of the differential-pair transistors be relative to the width of the CS transistor?

Figure P8.20 shows a MOS differential amplifer with the drain resistors implemented using diodeconnected PMOS transistors, and . Let and be matched, and and be matched.(a) Find the differential half-circuit and use it to derive an expression for in terms of and (b) Neglecting the effect of the output resistances find in terms of and (c) If and all four transistors have the same channel length, find that results in V/V.

Find the differential half-circuit for the differential amplifier shown in Fig. P8.21 and use it to derive an expression for the differential gain in terms of , , and . Neglect the Early effect. What is the gain with ? What is the value of (in terms of ) that reduces the gain to half this value?

The resistance in the circuit of Fig. P8.21 can be implemented by using a MOSFET operated in the triode region, as shown in Fig. P8.22. Here implements with the value of determined by the voltage at the gate of . (a) With V, and assuming that and are operating in saturation, what dc voltages appear at the sources of and Express these in terms of the overdrive voltage at which each of and operates, and . (b) For the situation in (a), what current flows in What overdrive voltage is operating at, in terms of , , and ? (c) Now consider the case and , where is a small signal. Convince yourself that now conducts current and operates in the triode region with a small What resistance does it have, expressed in terms of the overdrive voltage at which it is operating. This is the resistance Now if all three transistors have the same W/L, express in terms of , and (d) Find and hence that result in (i) (ii)

The circuit of Fig. P8.23 shows an effective way of implementing the resistance needed for the circuit in Fig. P8.21. Here is realized as the series equivalent of two MOSFETs and that are operated in the triode region, thus, + Assume that and are matched and operate in saturation at an overdrive voltage that corresponds to a drain bias current of I/2. Also, assume that and are matched. (a) With V, what dc voltages appear at the sources of and What current flows through and At what overdrive voltages are and operating? Find an expression for for each of and and hence for in terms of and . (b) Now with and where is a small signal, find an expression of the voltage gain in terms of and

Figure P8.24 shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2, respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following specifications: (a) Differential gain Ad = 80 V/V. (b) IREF = I = 100 A. (c) The dc voltage at the gates of Q6 and Q3 is +1.5 V. (d) The dc voltage at the gates of Q7, Q4, and Q5 is 1.5 V. The technology available is specified as follows: nCox = 3 pCox = 90 A/V2; Vtn = = 0.7 V, VAn = = 20 V. Specify the required value of R and the W / L ratios for all transistors. Also specify ID and at which each transistor is operating. For dc bias calculations you may neglect channel-length modulation.

A design error has resulted in a gross mismatch in the circuit of Fig. P8.25. Specifically, Q2 has twice the W / L ratio of Q1. If vid is a small sine-wave signal, find: (a) ID1 and ID2. (b) VOV for each of Q1 and Q2. (c) The differential gain Ad in terms of RD, I, and VOV.

For the cascode differential amplifier of Fig. 8.12(a) show that if all transistors have the same channel length and are operated at the same and assuming that , the differential gain is given by Now design the amplifier to obtain a differential gain of 1000 V/V. Use V. If V/m, specify the required channel length L. If is to be as high as possible but the power dissipation in the amplifier (in equilibrium) is to be limited to 1 mW, what bias current I would you use? Let

An NMOS differential pair is biased by a current source I = 0.2 mA having an output resistance RSS = 100 k. The amplifier has drain resistances RD = 10 k, using transistors with = 3 mA/V 2, and ro that is large. If the output is taken differentially and there is a 1% mismatch between the drain resistances, find , and CMRR.

For the differential amplifier shown in Fig. P8.2, let Q1 and Q2 have = 4 mA/V2, and assume that the bias current source has an output resistance of 30 k. Find , gm, , , and the CMRR (in dB) obtained with the output taken differentially. The drain resistances are known to have a mismatch of 2%.

The differential amplifier in Fig. P8.29 utilizes a resistor RSS to establish a 1-mA dc bias current. Note that this amplifier uses a single 5-V supply and thus the dc common-mode voltage VCM cannot be zero. Transistors Q1 and Q2 have = 2.5 mA/V2, Vt = 0.7 V, and = 0. (a) Find the required value of VCM. (b) Find the value of RD that results in a differential gain Ad of 8 V/V. (c) Determine the dc voltage at the drains. (d) Determine the common-mode gain . (Hint: You need to take into account.) (e) Use the common-mode gain found in (d) to determine the change in VCM that results in Q1 and Q2 entering the triode region.

The objective of this problem is to determine the common-mode gain and hence the CMRR of the differential pair arising from a simultaneous mismatch in gm and in RD. (a) Refer to the circuit in Fig. 8.13(a) and its equivalent in Fig. 8.14, and let the two drain resistors be denoted RD1 and RD2 where RD1 = RD + and RD2 = RD Also let gm1 = gm + and gm2 = gm Follow an analysis process similar to that used to derive Eq. (8.63) to show that Note that this equation indicates that RD can be deliberately varied to compensate for the initial variability in gm and RD, that is, to minimize Acm. (b) In a MOS differential amplifier for which RD = 5 k and RSS = 25 k, the common-mode gain is measured and found to be 0.002 V/V. Find the percentage change required in one of the two drain resistors so as to reduce Acm to zero (or close to zero).

A MOS differential amplifier utilizing a simple current source to provide the bias current I is found to have a CMRR of 60 dB. If it is required to raise the CMRR to 100 dB by adding a cascode transistor to the current source, what must the intrinsic gain of the cascode transistor be? If the cascode transistor is operated at V, what must its be? If for the specific technology utilized V/m, specify the channel length L of the cascode transistor.

For the differential amplifier of Fig. 8.16(a) let I = 0.5 mA, VCC = VEE = 2.5 V, VCM = 1 V, RC = 8 k, and = 100. Assume that the BJTs have vBE = 0.7 V at iC = 1 mA. Find the voltage at the emitters and at the outputs.

An npn differential amplifier with I = 0.5 mA, V, and k utilizes BJTs with and V at mA. If , find , and obtained with V, and with V. Assume that the current source requires a minimum of 0.3 V for proper operation.

An npn differential amplifier with I = 0.5 mA, V, and k utilizes BJTs with and V at mA. Assuming that the bias current is obtained by a simple current source and that all transistors require a minimum of 0.3 V for operation in the active mode, find the input common-mode range.

Repeat Exercise 8.9 for an input of 0.3 V.

An npn differential pair employs transistors for which mV at mA, and . The transistors leave the active mode at V. The collector resistors k and the power supplies are V. The bias current I = 20 A and is supplied with a simple current source. (a) For V, find , and . (b) Find the input common-mode range. (c) If find the value of that increases the current in by 10%.

Consider the BJT differential amplifier when fed with a common-mode voltage as shown in Fig. 8.16(a). As is often the case, the supply voltage may not be pure dc but might include a ripple component of small amplitude and a frequency of 120 Hz (see Section 4.5). Thus the supply voltage becomes . Find the ripple component of the collector voltages, and as well as of the difference output voltage . Comment on the differential amplifier response to this undesirable powersupply ripple.

Consider the differential amplifier of Fig. 8.15 and let the BJT be very large: (a) What is the largest input common-mode signal that can be applied while the BJTs remain comfortably in the active region with vCB = 0? (b) If an input difference signal is applied that is large enough to steer the current entirely to one side of the pair, what is the change in voltage at each collector (from the condition for which vid = 0)? (c) If the available power supply VCC is 2.5 V, what value of IRC should you choose in order to allow a common-mode input signal of 1.0 V? (d) For the value of IRC found in (c), select values for I and RC. Use the largest possible value for I subject to the constraint that the base current of each transistor (when I divides equally) should not exceed 2 A. Let

To provide insight into the possibility of nonlinear distortion resulting from large differential input signals applied tothe differential amplifier of Fig. 8.15, evaluate the normalized change in the current iE1, , for differential input signals vid of 5, 10, 20, 30, and 40 mV. Provide a tabulation of the ratio , which represents the proportional transconductance gain of the differential pair, versus vid. Comment on the linearity of the differential pair as an amplifier.

Design the circuit of Fig. 8.15 to provide a differential output voltage (i.e., one taken between the two collectors) of 1 V when the differential input signal is 10 mV. A current source of 1 mA and a positive supply of +5 V are available. What is the largest possible input common-mode voltage for which operation is as required? Assume

One of the trade-offs available in the design of the basic differential amplifier circuit of Fig. 8.15 is between the value of the voltage gain and the range of common-mode input voltage. The purpose of this problem is to demonstrate this trade-off. (a) Use Eqs. (8.73) and (8.74) to obtain iC1 and iC2 corresponding to a differential input signal of 5 mV (i.e., vB1 vB2 = 5 mV). Assume to be very high. Find the resulting voltage dif ference between the two collectors (vC2 vC1), and divide this value by 5 mV to obtain the voltage gain in terms of (IRC). (b) Find the maximum permitted value for VCM while the transistors remain comfortably in the active mode with vCB = 0. Express this maximum in terms of VCC and the gain, and hence show that for a given value of VCC, the higher the gain achieved, the lower the common-mode range. Use this expression to find VCMmax corresponding to a gain magnitude of 100, 200, 300, and 400 V/V. For each value, also give the required value of IRC and the value of RC for I = 1 mA. As an example, discuss what can be achieved with VCC = 10 V.

For the circuit in Fig. 8.15, assuming = 1 and IRC = 5 V, use Eqs. (8.70) and (8.71) to find iC1 and iC2, and hence determine vod = vC2 vC1 for input differential signals vid vB1 vB2 of 5 mV, 10 mV, 15 mV, 20 mV, 25 mV, 30 mV, 35 mV, and 40 mV. Plot vo versus vid, and hence comment on the amplifier linearity. As another way of visualizing linearity, determine the gain versus vid. Comment on the resulting graph.

In a differential amplifier using a 3-mA emitter bias current source, the two BJTs are not matched. Rather, one has twice the emitter junction area of the other. For a differential input signal of zero volts, what do the collector currents become? What difference input is needed to equalize the collector currents? Assume

This problem explores the linearization of the transfer characteristics of the differential pair achieved by including emitter-degeneration resistances in the emitters (see Fig. 8.18). Consider the case I = 200 A with the transistors exhibiting mV at mA and assume . (a) With no emitter resistances what value of results when (b) With no emitter resistances use the large-signal model to find and when mV. (c) Now find the value of that will result in the same and as in (b) but with mV. Use the largesignal model. (d) Calculate the effective transconductance as the inverse of the total resistances in the emitter circuits in the cases without and with the s. By what factor is reduced? How does this factor relate to the increase in Comment.

A BJT differential amplifier uses a 200-A bias current. What is the value of gm of each device? If is 150, what is the differential input resistance?

Design the basic BJT differential amplifier circuit of Fig. 8.19 to provide a differential input resistance of at least 10 k and a differential voltage gain of 100 V/V. The transistor is specified to be at least 100. The available positive power supply is5 V.

For a differential amplifier to which a total difference signal of 10 mV is applied, what is the equivalent signal to its corresponding CE half-circuit? If the emitter current source I is 100 A, what is re of the half-circuit? For a load resistance of 10 k in each collector, what is the half-circuit gain? What magnitude of signal output voltage would you expect at each collector? Between the two collectors?

A BJT differential amplifier is biased from a 1-mA constant-current source and includes a 200- resistor in each emitter. The collectors are connected to VCC via 12-k resistors. A differential input signal of 0.1 V is applied between the two bases. (a) Find the signal current in the emitters (ie) and the signal voltage vbe for each BJT. (b) What is the total emitter current in each BJT? (c) What is the signal voltage at each collector? Assume =1. (d) What is the voltage gain realized when the output is taken between the two collectors?

Design a BJT differential amplifier to amplify a differential input signal of 0.2 V and provide a differential output signal of 5 V. To ensure adequate linearity, it is required to limit the signal amplitude across each baseemitter junction to a maximum of 5 mV. Another design requirement is that the differential input resistance be at least 50 k. The BJTs available are specified to have 100. Give the circuit configuration and specify the values of all its components.

Design a bipolar differential amplifier such as that in Fig. 8.19 to operate from V power supplies and to provide differential gain of 40 V/V. The power dissipation in the quiescent state should not exceed 2 mW. (a) Specify the values of I and What dc voltage appears at the collectors? (b) If what is the input differential resistance? (c) For mV, what is the signal voltage at each of the collectors? (d) For the situation in (c), what is the maximum allowable value of the input common mode voltage, ? Recall that to maintain an npn BJT in saturation, should not exceed by more than 0.4 V.

In this problem we explore the trade-off between input common-mode range and differential gain in the design of the bipolar BJT. Consider the bipolar differential amplifier in Fig. 8.15 with the input voltages (a) Bearing in mind that for a BJT to remain in the active mode, should not exceed 0.4 V, show that when has a peak , the maximum input common-mode voltage is given by (b) For the case V and mV, use the relationship above to determine for the case V/V. Also find the peak output signal and the required value of . Now if the power dissipation in the circuit is to be limited to 5 mW in the quiescent state (i.e., with vid = 0), find I and (Remember to include the power drawn from the negative power supply V.) (c) If is to be 0 V, and all other conditions remain the same, what gain is achievable?

For the differential amplifier of Fig. 8.15, let V and V. Find the differential gain . Sketch and clearly label the waveforms for the total collector voltages and for the following two cases:

Consider a bipolar differential amplifier in which the collector resistors are replaced with simple current sources implemented using pnp transistors. Sketch the circuit and give its differential half-circuit. If V for all transistors, find the differential voltage gain achieved.

For each of the emitter-degenerated differential amplifiers shown in Fig. P8.54, find the differential halfcircuit and derive expressions for the differential gain and differential input resistance For each circuit, what dc voltage appears across the bias current source(s) in the quiescent state (i.e., with ). Hence, which of the two circuits will allow a larger negative

Consider a bipolar differential amplifier that, in addition to the collector resistances has a load resistance connected between the two collectors. What does the differential gain become?

A bipolar differential amplifier having resistance inserted in series with each emitter (as in Fig. 8.21) is biased with a constant current I. When both input terminals are grounded, the dc voltage measured across each is found to be 4 and that measured across each is found to be 40 . What differential voltage gain do you expect the amplifier to have?

A bipolar differential amplifier with emitter degeneration resistances and is fed with the arrangement shown in Fig. P8.57. Derive an expression for the overall differential voltage gain If is of such a value that find the gain in terms of , and . Now if is doubled, by what factor does increase?

A particular differential amplifier operates from an emitter current source whose output resistance is 0.5 M. What resistance is associated with each common-mode half-circuit? For collector resistors of 20 k and 1% tolerance, what is the resulting common-mode gain for output taken (a) singleendedly? and (b) differentially?

Find the voltage gain and the input resistance of the amplifier shown in Fig. P8.59 assuming

Find the voltage gain and input resistance of the amplifier in Fig. P8.60 assuming that

Derive an expression for the small-signal voltage gain of the circuit shown in Fig. P8.61 in two different ways: (a) as a differential amplifier (b) as a cascade of a common-collector stage Q1 and a common-base stage Q2 Assume that the BJTs are matched and have a current gain , and neglect the Early effect. Verify that both approaches lead to the same result.

The differential amplifier circuit of Fig. P8.62 utilizes a resistor connected to the negative power supply to establish the bias current I. (a) For vB1 = vid 2 and vB2 = vid 2, where vid is a small signal with zero average, find the magnitude of the differential gain, . (b) For vB1 = vB2 = vicm, where vicm has a zero average, find the magnitude of the common-mode gain, . (c) Calculate the CMRR. (d) If vB1 = 0.1 sin 2 60t + 0.005 sin 2 1000t volts, and vB2 = 0.1 sin 2 60t 0.005 sin 2 1000t, volts, findvo.

For the differential amplifier shown in Fig. P8.63, identify and sketch the differential half-circuit and the commonmode half-circuit. Find the differential gain, the differential input resistance, the common-mode gain assuming the resistances RC have 1% tolerance, and the common-mode input resistance. For these transistors,

Consider the basic differential circuit in which the transistors have = 100 and VA = 100 V, with I = 0.5 mA, REE = 200 k, and RC = 20 k. The collector resistances are matched to within 1%. Find: (a) the differential gain (b) the differential input resistance (c) the common-mode gain (d) the common-mode rejection ratio (e) the input common-mode resistance

In a differential-amplifier circuit resembling that shown in Fig. 8.26(a), the current generator represented by I and REE consists of a simple common-emitter transistor operating at 100 A. For this transistor, and those used in the differential pair, VA = 20 V and = 50. What commonmode input resistance would result?

A bipolar differential amplifier with I = 0.5 mA utilizes transistors for which V and The collector resistances k and are matched to within 2%. Find: (a) the differential gain (b) the common-mode gain and the CMRR if the bias current I is generated using a simple current mirror (c) the common-mode gain and the CMRR if the bias current I is generated using a Wilson mirror. (Refer to Eq. 7.81 for Ro of the Wilson mirror.)

It is required to design a differential amplifier to provide the largest possible signal to a pair of 10-k load resistances. The input differential signal is a sinusoid of 5-mV peak amplitude, which is applied to one input terminal while the other input terminal is grounded. The power supply available is 10 V. To determine the required bias current I, derive an expression for the total voltage at each of the collectors in terms of VCC and I in the presence of the input signal. Then impose the condition that both transistors should remain well out of saturation with a minimum vCB of approximately 0 V. Thus determine the required value of I. For this design, what differential gain is achieved? What is the amplitude of the signal voltage obtained between the two collectors? Assume

Design a BJT differential amplifier that provides two single-ended outputs (at the collectors). The amplifier is to have a differential gain (to each of the two outputs) of at least 100 V/V, a differential input resistance 10 k, and a common-mode gain (to each of the two outputs) no greater than 0.1 V/V. Use a 2-mA current source for biasing. Give the complete circuit with component values and suitable power supplies that allow for 2 V swing at each collector. Specify the minimum value that the output resistance of the bias current source must have. The BJTs available have 100. What is the value of the input commonmode resistance when the bias source has the lowest acceptable resistance?

When the output of a BJT differential amplifier is taken differentially, its CMRR is found to be 40 dB higher than when the output is taken single-endedly. If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch be (in percent)?

In a particular BJT differential amplifier, a production error results in one of the transistors having an emitterbase junction area that is twice that of the other. With the inputs grounded, how will the emitter bias current split between the two transistors? If the output resistance of the current source is 500 k and the resistance in each collector (RC) is 12 k, find the common-mode gain obtained when the output is taken differentially. Assume

An NMOS differential pair is to be used in an amplifier whose drain resistors are 10 k 1%. For the pair, W/L = 4 mA/V2. A decision is to be made concerning the bias current I to be used, whether 160 A or 360 A. Contrast the differential gain and input offset voltage for the two possibilities.

An NMOS amplifier, whose designed operating point is at VOV = 0.2 V, is suspected to have a variability of Vt of 5 mV, and of W/L and RD (independently) of 2%. What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the output offset to zero and thereby compensate for the uncertainties (including that of the other RD), what percentage change from nominal would you require? If by selection you reduced the contribution of the worst cause of offset by a factor of 10, what change in RD would be needed?

An NMOS differential pair operating at a bias current I of 100 A uses transistors for which and W/L = 10. Find the three components of input offset voltage under the conditions that = 5%, (W/L)(W/L) = 5%, and In the worst case, what might the total offset be? For the usual case of the three effects being independent, what is the offset likely to be?

A bipolar differential amplifier uses two wellmatched transistors but collector load resistors that are mismatched by 8%. What input offset voltage is required to reduce the differential output voltage to zero?

A bipolar differential amplifier uses two transistors whose scale currents IS differ by 10%. If the two collector resistors are well matched, find the resulting input offset voltage.

Modify Eq. (8.119) for the case of a differential amplifier having a resistance RE connected in the emitter of each transistor. Let the bias current source be I.

A differential amplifier uses two transistors whose values are 1 and 2. If everything else is matched, show that the input offset voltage is approximately . Evaluate VOS for 1 = 100 and 2 = 200. Assume the differential source resistance to be zero.

Two possible differential amplifier designs are considered, one using BJTs and the other MOSFETs. In both cases, the collector (drain) resistors are maintained within % of nominal value. The MOSFETs are operated at mV. What input offset voltage results in each case? What does the MOS become if the devices are increased in width by a factor of 4?

A differential amplifier uses two transistors having VA values of 100 V and 300 V. If everything else is matched, find the resulting input offset voltage. Assume that the two transistors are intended to be biased at a VCE of about 10 V.

A differential amplifier is fed in a balanced or pushpull manner, and the source resistance in series with each base is Rs. Show that a mismatch Rs between the values of the two source resistances gives rise to an input offset voltage of approximately (I

One approach to offset correction involves the adjustment of the values of RC1 and RC2 so as to reduce the differential output voltage to zero when both input terminals are grounded. This offset-nulling process can be accomplished by utilizing a potentiometer in the collector circuit, as shown in Fig. P8.81. We wish to find the potentiometer setting, represented by the fraction x of its value connected in series with RC1, that is required for nulling the output offset voltage that results from: (a) RC1 being 4% higher than nominal and RC2 4% lower than nominal (b) Q1 having an area 20% larger than that of Q2

A differential amplifier for which the total emitter bias current is 500 A uses transistors for which is specified to lie between 80 and 200. What is the largest possible input bias current? The smallest possible input bias current? The largest possible input offset current?

In a particular BJT differential amplifier, a production error results in one of the transistors having an emitter base junction area twice that of the other. With both inputs grounded, find the current in each of the two transistors and hence the dc offset voltage at the output, assuming that the collector resistances are equal. Use small-signal analysis to find the input voltage that would restore current balance to the differential pair. Repeat using large-signal analysis and compare results.

A large fraction of mass-produced differentialamplifier modules employing 20-k collector resistors is found to have an input offset voltage ranging from +3 mV to 3 mV. By what amount must one collector resistor be adjusted to reduce the input offset to zero? If an adjustment mechanism is devised that raises one collector resistor while correspondingly lowering the other, what resistance change is needed? If a potentiometer connected as shown in Fig. P8.81 is used, what value of potentiometer resistance (specified to 1 significant digit) is needed?

In an active-loaded differential amplifier of the form shown in Fig. 8.32(a), all transistors are characterized by k W/L = 3.2 mA/V2, and Find the bias current I for which the gain = 100 V/V.

It is required to design the active-loaded differential MOS amplifier of Fig. 8.32 to obtain a differential gain of 50V/V. The technology available provides nCox = A/V2, V, and V/m and operates from V supplies. Use a bias current I = 200A and operate all devices at V. (a) Find the W/L ratios of the four transistors. (b) Specify the channel length required of all transistors. (c) If , what is the allowable range of ? (d) If I is delivered by a simple NMOS current source operated at the same and having the same channel length as the other four transistors, determine the CMRR obtained.

Consider the active-loaded MOS differential amplifier of Fig. 8.32(a) in two cases: (a) Current source I is implemented with a simple current mirror. (b) Current source I is implemented with the modified Wilson current mirror shown in Fig. P8.87. Recalling that for the simple mirror and for the Wilson mirror and assuming that all transistors have the same and show that for case (a) and for case (b) where VOV is the overdrive voltage that corresponds to a drain current of For I = 1 mA, and find CMRR for both cases.

Consider an active-loaded differential amplifier such as that shown in Fig. 8.32(a) with the bias current source implemented with the modified Wilson mirror of Fig. P8.87 with I = 200 A. The transistors have and k W/L = 5 mA/V2. What is the lowest value of the total power supply (VDD + VSS) that allows each transistor to operate with

(a) Sketch the circuit of an active-loaded MOS differential amplifier in which the input transistors are cascoded and a cascode current mirror is used for the load. (b) Show that if all transistors are operated at an overdrive voltage VOV and have equal Early voltages the gain is given by Evaluate the gain for VOV = 0.25 V and VA = 20 V.

Figure P8.90 shows the active-loaded MOS differential amplifier prepared for small-signal analysis. To help the reader we have already indicated approximate values for some of the node voltages. For instance, the output voltage , which we have derived in the text. The voltage at the common sources has been found to be approximately , which is very far from the virtual ground one might assume. Also, the voltage at the gate of the mirror is approximately confirming our contention that the voltage there is vastly different from the output voltage, hence the lack of balance in the circuit and the unavailability of a differential half-circuit. Find the currents labeled to Determine their values in the sequence of their numbering and reflect on the results. You will find that there is some inconsistency, which is a result of the approximations we have made. Note that all transistors are assumed to be operating at the same .

An active-loaded NMOS differential amplifier operates with a bias current I of 100 A. The NMOS transistors are operated at V and the PMOS devices at V. The Early voltages are 20 V for the NMOS and 12 V for the PMOS transistors. Find and For what value of load resistance is the gain reduced by a factor of 2?

This problem investigates the effect of transistor mismatches on the input offset voltage of the active-loaded MOS differential amplifier of Fig. 8.32(a). For this purpose, ground both input terminals and short-circuit the output node to ground. (a) If the amplifying transistors and exhibit a W/L mismatch of find the resulting short-circuit output current and hence show that the corresponding is given by where is the overdrive voltage at which and are operating. (b) Repeat for a mismatch in the ratios of the mirror transistor and to show that the corresponding is given by where is the overdrive voltage at which and are operating. (c) For a circuit in which all transistors are operated at V and all W/L ratios are accurate to within % of nominal, find the worst-case total offset voltage .

The differential amplifier in Fig. 8.37(a) is operated with I = 400 A, with devices for which VA = 16 V and = 100. What differential input resistance, output resistance, equivalent transconductance, and open-circuit voltage gain would you expect? What will the voltage gain be if the input resistance of the subsequent stage is equal to Rid of this stage?

Design the circuit of Fig. 8.37(a) using a basic current mirror to implement the current source I. It is required that the equivalent transconductance be 4 mA/V. Use 5-V power supplies and BJTs that have = 125 and VA = 100 V. Give the complete circuit with component values and specify the differential input resistance Rid, the output resistance Ro, the open-circuit voltage gain Ad, the input bias current, the input common-mode range, the common-mode gain, and the CMRR.

Repeat the design of the amplifier specified in Problem 8.94 utilizing a Widlar current source [Fig. 7.36] to supply the bias current. Assume that the largest resistance available is 2 k.

Modify the design of the amplifier in Problem 8.94 by connecting emitter-degeneration resistances of values that result in Rid = 125 k. What does Ad become?

An active-loaded bipolar differential amplifier such as that shown in Fig. 8.37(a) has I = 0.5 mA, VA = 30 V, and = 150. Find Gm, Ro, Ad, and Rid. If the bias-current source is implemented with a simple npn current mirror, find REE, Acm, and CMRR. If the amplifier is fed differentially with a source having a total of 20 k resistance (i.e., 10 k in series with the base lead of each of Q1 and Q2), find the overall differential voltage gain.

This problem provides a general approach to the determination of the common-mode gain of the activeloaded differential amplifier of either type (MOS and BJT). The method is illustrated in Fig. P8.98, in which we have replaced each of and together with their source (emitter) resistances with a controlled source and an output resistance For the MOS case, ; for the bipolar case. Usually and are much larger than the resistances at the respective nodes and can be neglected. The current mirror has been replaced by an equivalent circuit consisting of an input resistance a controlled source with current gain and an output resistance (a) Show that the common-mode gain is given approximately by (b) For the simple MOS mirror consisting of and as in Fig. 8.32(a), show that and hence derive the expression for the common-mode gain given in Eq. (8.146). (c) For the simple bipolar mirror consisting of and as in Fig. 8.37(a), show that and hence derive the expression for the CM gain given in Eq. (8.165).

For the active-loaded MOS differential pair, replacing the simple current-mirror load by the Wilson mirror of Fig. 7.35(a), find the CM gain. [Hint: Use the general formula in Problem 8.98, namely, where is the output resistance of the mirror and is its current transfer ratio. Note, however, that this formula will overestimate because we are neglecting

For the active-loaded bipolar differential pair, replacing the simple current-mirror load by the base-currentcompensated mirror of Fig. 7.33, find the expected systematic input offset voltage. Evaluate for

For the active-loaded bipolar differential pair, replacing the simple current-mirror load by the Wilson mirror of Fig. 7.34(a), find the expected systematic input offset voltage. Evaluate

Figure P8.102 shows a differential cascode amplifier with an active load formed by a Wilson current mirror. Utilizing the expressions derived in Chapter 7 for the output resistance of a bipolar cascode and the output resistance of the Wilson mirror, and assuming all transistors to be identical, show that the differential voltage gain Ad is given approximately by

Consider the bias design of the Wilson-loaded cascode differential amplifier shown in Fig. P8.102. (a) What is the largest signal voltage possible at the output without Q7 saturating? Assume that the CB junction conducts when the voltage across it exceeds 0.4 V. (b) What should the dc bias voltage established at the output (by an arrangement not shown) be in order to allow for positive output signal swing of 1.5 V? (c) What should the value of VBIAS be in order to allow for a negative output signal swing of 1.5 V? (d) What is the upper limit on the input common-mode voltage vCM?

Figure P8.104 shows a modified cascode differential amplifier. Here Q3 and Q4 are the cascode transistors. However, the manner in which Q3 is connected with its base current feeding the current mirror Q7Q8 results in very

For the folded-cascode differential amplifier of Fig. 8.40, find the value of VBIAS that results in the largest possible positive output swing, while keeping Q3, Q4, and the pnp transistors that realize the current sources out of saturation. Assume VCC = VEE = 5 V. If the dc level at the output is 0 V, find the maximum allowable output signal swing. For I = 0.4 mA, P = 50, N = 150, and VA = 120 V find Gm, Ro4, Ro5, Ro, and Ad.

For the BiCMOS differential amplifier in Fig. P8.106 let VDD = VSS = 3 V, I = 0.4 mA, for p-channel MOSFETs is 10 V, for npn transistors is 30 V. Find Gm, Ro, and Ad.

For the BiCMOS differential amplifier in Fig. P8.106 let VDD = VSS = 3 V, I = 0.4 mA, for p-channel MOSFETs is 10 V, for npn transistors is 30 V. Find Gm, Ro, and Ad.

The two-stage CMOS op amp in Fig. P8.108 is fabricated in a 0.18-m technology having 400 A/V2, V. (a) With A and B grounded, perform a dc design that will result in each of Q1, Q2, Q3, and Q4 conducting a drain current of 200 A. Design so that all transistors operate at 0.2 V-overdrive voltages. Specify the W/L ratio required for each MOSFET. Present your results in tabular form. What is the dc voltage at the output (ideally)? (b) Find the input common-mode range. (c) Find the allowable range of the output voltage (s) With and , find the voltage gain . Assume an Early voltage of 5 V.

In a particular design of the CMOS op amp of Fig. 8.41 the designer wishes to investigate the effects of increasing the W / L ratio of both Q1 and Q2 by a factor of 4. Assuming that all other parameters are kept unchanged, refer to Example 8.5 to help you answer the following questions: (a) Find the resulting change in and in gm of Q1 and Q2. (b) What change results in the voltage gain of the input stage? In the overall voltage gain? (c) What is the effect on the input offset voltages? (You might wish to refer to Section 8.4).

Consider the amplifier of Fig. 8.41, whose parameters are specified in Example 8.5. If a manufacturing error results in the W / L ratio of Q7 being 50 / 0.8, find the current that Q7 will now conduct. Thus find the systematic offset voltage that will appear at the output. (Use the results of Example 8.5.) Assuming that the open-loop gain will remain approximately unchanged from the value found in Example 8.5, find the corresponding value of input offset voltage, VOS.

Consider the input stage of the CMOS op amp in Fig. 8.41 with both inputs grounded. Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q3 and Q4 have a mismatch Show that a current gm3 appears at the output of the first stage. What is the corresponding input offset voltage?

Figure P8.112 shows a bipolar op-amp circuit that resembles the CMOS op amp of Fig. 8.41. Here, the input differential pair Q1Q2 is loaded in a current mirror formed by Q3 and Q4. The second stage is formed by the currentsource-loaded common-emitter transistor Q5. Unlike the CMOS circuit, here there is an output stage formed by the emitter follower Q6. The function of capacitor CC will be explained later in Chapter 10. All transistors have = 100, = 0.7 V, and (a) For inputs grounded and output held at 0 V (by negative feedback, not shown) find the emitter currents of all transistors. (b) Calculate the gain of the amplifier with RL = 10 k.

It is required to design the circuit of Fig. 8.42 to provide a bias current IB of 225 A with Q8 and Q9 as matched devices having W/L = 60/0.5. Transistors Q10, Q11, and Q13 are to be identical and must have the same gm as Q8 and Q9. Transistor Q12 is to be four times as wide as Q13. Let and VDD = VSS = 1.5 V. Find the required value of RB. What is the voltage drop across RB? Also specify the W / L ratios of Q10, Q11, Q12, and Q13 and give the expected dc voltages at the gates of Q12, Q10, and Q8.

A BJT differential amplifier, biased to have re = 100 and utilizing two 100- emitter resistors and 5-k loads, drives a second differential stage biased to have re = 50 . All BJTs have = 100. What is the voltage gain of the first stage? Also find the input resistance of the first stage, and the current gain from the input of the first stage to the collectors of the second stage.

In the multistage amplifier of Fig. 8.43, emitter resistors are to be introduced100 in the emitter lead of each of the first-stage transistors and 25 for each of the secondstage transistors. What is the effect on input resistance, the voltage gain of the first stage, and the overall voltage gain? Use the bias values found in Example 8.6.

Consider the circuit of Fig. 8.43 and its output resistance. Which resistor has the most effect on the output resistance? What should this resistor be changed to if the output resistance is to be reduced by a factor of 2? What will the amplifier gain become after this change? What other change can you make to restore the amplifier gain to approximately its prior value?

(a) If, in the multistage amplifier of Fig. 8.43, the resistor R5 is replaced by a constant-current source 1 mA, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become? Assume that the output resistance of the current source is very high. Use the results of Example 8.7. (b) With the modification suggested in (a), what is the effect of the change on output resistance? What is the overall gain of the amplifier when loaded by 100 to ground? The original amplifier (before modification) has an output resistance of 152 and a voltage gain of 8513 V/V. What is its gain when loaded by 100 ? Comment. Use

Figure P8.118 shows a three-stage amplifier in which the stages are directly coupled. The amplifier, however, utilizes bypass capacitors, and, as such, its frequency response falls off at low frequencies. For our purposes here, we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest. (a) Find the dc bias current in each of the three transistors. Also find the dc voltage at the output. Assume = 100, and neglect the Early effect. (b) Find the input resistance and the output resistance. (c) Use the current-gain method to evaluate the voltage gain vo vi.

The MOS differential amplifier shown in Fig. P8.119 utilizes three current mirrors for signal transmission: has a transmission factor of 2 [i.e., ], has a transmission factor of 1, and has a transmission factor of 2. All transistors are sized to operate at the same overdrive voltage, . All transistors have the same Early voltage . (a) Provide in tabular form the values of and of each of the eight transistors in terms of I, and . (b) Show that the differential voltage gain is given by (c) Show that the CM gain is given by where is the output resistance of the bias current source I. [Hint: Replace each of and together with their source resistance with a controlled current-source and an output resistance. For each current mirror, the current transfer ratio is given by (ideal) where and are the parameters of the input transistor of the mirror.](d) If the current-source I is implemented using a simple mirror and the MOS transistor is operated at the same , show that the CMRR is given by (e) Find the input CM range and the output linear range in terms of , and

For the circuit shown in Fig. P8.120, which uses a folded cascode involving transistor Q3, all transistors have for the currents involved, VA = 200 V, and = 100. The circuit is relatively conventional except for Q5, which operates in a Class B mode (we will study this in Chapter 11) to provide an increased negative output swing for low-resistance loads. (a) Perform a bias calculation assuming high , VA = , v+ = v = 0 V, and vO is stabilized by feedback to about 0 V. Find R so that the reference current IREF is 100 A. What are the voltages at all the labeled nodes? (b) Provide in tabular form the bias currents in all transistors together with gm and ro for the signal transistors (Q1, Q2, Q3, Q4, and Q5) and ro for QC, QD, and QG. (c) Now, using = 100, find the voltage gain vo (v+ v), and in the process, verify the polarity of the input terminals. (d) Find the input and output resistances. (e) Find the input common-mode range for linear operation. (f) For no load, what is the range of available output voltages, assuming (g) Now consider the situation with a load resistance connected from the output to ground. At the positive and negative limits of the output signal swing, find the smallest load resistance that can be driven if one or the other of Q1 or Q2 is allowed to cut off.

In the CMOS op amp shown in Fig. P8.121, all MOS devices have nCox = 2 pCox = 40 A/V2, and L = 5 m. Device widths are indicated on the diagram as multiples of W, where W = 5 m. (a) Design R to provide a 10-A reference current. (b) Assuming vO = 0 V, as established by external feedback, perform a bias analysis, finding all the labeled node voltages, VGS and ID for all transistors. (c) Provide in table form ID, VGS, gm, and ro for all devices. (d) Calculate the voltage gain the input resistance, and the output resistance. (e) What is the input common-mode range? (f) What is the output signal range for no load? (g) For what load resistance connected to ground is the output negative voltage limited to 1 V before Q7 begins to conduct? (h) For a load resistance one-tenth of that found in (g), what is the output signal swing?