A class A emitter follower, biased using the circuit shown

A class A emitter follower, biased using the circuit shown in Fig. 11.2, uses VCC = 5 V, R = RL = 1 k, with all transistors (including Q3) identical. Assume VBE = 0.7 V, VCEsat = 0.3 V, and to be very large. For linear operation, what are the upper and lower limits of output voltage, and thecorresponding inputs? How do these values change if the emitterbase junction area of Q3 is made twice as big as that of Q2? Half as big?

A source-follower circuit using NMOS transistors is constructed following the pattern shown in Fig. 11.2. All three transistors used are identical, with Vt = 1 V and nCox = 20 mA/V2; VCC = 5 V, R = RL = 1 k. For linear operation, what are the upper and lower limits of the output voltage, and the corresponding inputs?

Using the follower configuration shown in Fig. 11.2 with 9-V supplies, provide a design capable of 7-V outputs with a 1-k load, using the smallest possible total supply current. You are provided with four identical, high BJTs and a resistor of your choice.

An emitter follower using the circuit of Fig. 11.2, for which the output voltage range is 5 V, is required using VCC = 10 V. The circuit is to be designed such that the current variation in the emitter-follower transistor is no greater than a factor of 10, for load resistances as low as 100 . What is the value of R required? Find the incremental voltage gain of the resulting follower at vO = +5, 0, and 5 V, with a 100- load. What is the percentage change in gain over this range of vO?

Consider the operation of the follower circuit of Fig. 11.2 for which when driven by a square wave such that the output ranges from +VCC to VCC (ignoring VCEsat). For this situation, sketch the equivalent of Fig. 11.4 for vO, iC1, and pD1. Repeat for a square-wave output that has peak levels of What is the average power dissipation in Q1 in each case? Compare these results to those for sine waves of peak amplitude VCC and respectively.

Consider the situation described in Problem 11.5. For square-wave outputs having peak-to-peak values of 2VCC and VCC, and for sine waves of the same peak-to-peak values, find the average power loss in the current-source transistor Q2.

Reconsider the situation described in Exercise 11.3 for variation in VCCspecifically for VCC = 16 V, 12 V, 10 V, and 8 V. Assume VCEsat is nearly zero. What is the powerconversion efficiency in each case?

Consider the circuit of a complementary-BJT class B output stage. For what amplitude of input signal does the crossover distortion represent a 10% loss in peak amplitude?

Consider the feedback configuration with a class B output stage shown in Fig. 11.9. Let the amplifier gain A0 = 100 V/V. Derive an expression for vO versus vI, assuming that Sketch the transfer characteristic vO versus vI, and compare it with that without feedback.

Consider the class B output stage, using enhancement MOSFETs, shown in Fig. P11.10. Let the devices have and Cox = 2 mA/V2. With a 10-kHz sine-wave input of 5-V peak and a high value of load resistance, what peak output would you expect? What fraction of the sine-wave period does the crossover interval represent? For what value of load resistor is the peak output voltage reduced to half the input?

Consider the complementary-BJT class B output stage and neglect the effects of finite VBE and VCEsat. For 10-V power supplies and a 100- load resistance, what is the maximum sine-wave output power available? What supply power corresponds? What is the power-conversion efficiency? For output signals of half this amplitude, find the output power, the supply power, and the power-conversion efficiency.

A class B output stage operates from 5-V supplies. Assuming relatively ideal transistors, what is the output voltage for maximum power-conversion efficiency? What is the output voltage for maximum device dissipation? If each of the output devices is individually rated for 1-W dissipation, and a factorof-2 safety margin is to be used, what is the smallest value of load resistance that can be tolerated, if operation is always at full output voltage? If operation is allowed at half the full output voltage, what is the smallest load permitted? What is the greatest possible output power available in each case?

A class B output stage is required to deliver an average power of 100 W into a 16- load. The power supply should be 4 V greater than the corresponding peak sine-wave output voltage. Determine the power-supply voltage required (to the nearest volt in the appropriate direction), the peak current from each supply, the total supply power, and the power-conversion efficiency. Also, determine the maximum possible power dissipation in each transistor for a sine-wave input.

Consider the class B BJT output stage with a squarewave output voltage of amplitude across a load RL and employing power supplies VSS. Neglecting the effects of finite VBE and VCEsat, determine the load power, the supply power, the power-conversion efficiency, the maximum attainable power-conversion efficiency and the corresponding value of and the maximum available load power. Also find the value of at which the power dissipation in the transistors reaches its peak, and the corresponding value of power-conversion efficiency.

Design the quiescent current of a class AB BJT output stage so that the incremental voltage gain for vI in the vicinity of the origin is in excess of 0.98 V/V for loads larger than 100 . Assume that the BJTs have VBE of 0.7 V at a current of 100 mA and determine the value of VBB required.

For the class AB output stage considered in Example 11.3, add two columns to the table of results as follows: the total input current drawn from ( , mA); and the large-signal input resistance . Assume . Compare the values of to the approximate value obtained using the resistance reflection rule,

In this problem we investigate an important trade-off in the design of the class AB output stage of Fig. 11.11: Increasing the quiescent current reduces the nonlinearity of the transfer characteristic at the expense of increased quiescent power dissipation. As a measure of nonlinearity, we use the maximum deviation of the stage incremental gain, which occurs at , namely (a) Show that is given by which for can be approximated by (b) If the stage is operated from power supplies of , find the quiescent power dissipation, . (c) Show that for given and , the product of the quiescent power dissipation and the gain error is a constant given by (d) For V and , find the required values of and if is to be 5%, 2%, and 1%.

A class AB output stage, resembling that in Fig. 11.11 but utilizing a single supply of +10 V and biased at VI = 6 V, is capacitively coupled to a 100- load. For transistors for which at 1 mA and for a bias voltage VBB = 1.4 V, what quiescent current results? For a step change in output from 0 to 1 V, what input step is required? Assuming transistor saturation voltages of zero, find the largest possible positive-going and negative-going steps at the output.

Consider the diode-biased class AB circuit of Fig. 11.14. For IBIAS = 100 A, find the relative size (n) that should be used for the output devices (in comparison to the biasing devices) to ensure that an output resistance of 10 or less is obtained in the quiescent state. Neglect the resistance of the biasing diodes.

A class AB output stage using a two-diode bias network as shown in Fig. 11.14 utilizes diodes having the same junction area as the output transistors. For VCC = 10 V, IBIAS = 0.5 mA, RL = 100 , N = 50, and what is the quiescent current? What are the largest possible positive and negative output signal levels? To achieve a positive peak output level equal to the negative peak level, what value of N is needed if IBIAS is not changed? What value of IBIAS is needed if N is held at 50? For this value, what does IQ become?

A class AB output stage using a two-diode bias network as shown in Fig. 11.14 utilizes diodes having the same junction area as the output transistors. At a room temperature of about 20C the quiescent current is 1 mA and Through a manufacturing error, the thermal coupling between the output transistors and the biasing diode-connected transistors is omitted. After some output activity, the output devices heat up to 70C while the biasing devices remain at 20C. Thus, while the VBE of each device remains unchanged, the quiescent current in the output devices increases. To calculate the new current value, recall that there are two effects: IS increases by about and changes, where T = (273 + temperature in C), and VT = 25 mV only at 20C. However, you may assume that N remains almost constant. This assumption is based on the fact that increases with temperature but decreases with current. What is the new value of IQ? If the power supply is 20 V, what additional power is dissipated? If thermal runaway occurs, and the temperature of the output transistors increases by 10C for every watt of additional power dissipation, what additional temperature rise and current increase result?

Repeat Example 11.5 for the situation in which the peak positive output current is 200 mA. Use the same general approach to safety margins. What are the values of R1 and R2 you have chosen?

A VBE multiplier is designed with equal resistances for nominal operation at a terminal current of 1 mA, with half the current flowing in the bias network. The initial design is based on = and VBE = 0.7 V at 1 mA. (a) Find the required resistor values and the terminal voltage. (b) Find the terminal voltage that results when the terminal current increases to 2 mA. Assume = . (c) Repeat (b) for the case the terminal current becomes 10mA. (d) Repeat (c) using the more realistic value of

(a) Show that for the class AB circuit in Fig. 11.17, the small-signal output resistance in the quiescent state is given by which for matched devices becomes (b) For a circuit that utilizes MOSFETs with and find the voltage that results in

(a) For the circuit in Fig. 11.17 in which and are matched, and and are matched, show that the small-signal voltage gain at the quiescent condition is given by where is the transconductance of each of and and where channel-length modulation is neglected. (b) For the case , , kn = kp = nk1 = nk2, where k = Cox(W/L), and find the ratio n that results in an incremental gain of 0.98. Also find the quiescent current

Design the circuit of Fig. 11.17 to operate at IQ = with . Let Design so that and are matched and and are matched, and that in the quiescent state each operates at an overdrive voltage of 0.2 V. (a) Specify the W/L ratio for each of the four transistors. (b) In the quiescent state with , what must be? (c) If is required to supply a maximum load current of 10 mA, find the maximum allowable output voltage. Assume that the transistor supplying needs a minimum of 0.2 V to operate properly.

For the CMOS output stage of Fig. 11.19 with for each of and at the quiescent point, and find the output resistance at the quiescent point.

(a) Show that for the CMOS output stage of Fig. 11.19, (b) For a stage that drives a load resistance of 100 with a gain error of less than 5%, find the overdrive voltage at which and should be operated. Let and .

It is required to design the circuit of Fig. 11.19 to drive a load resistance of 50 while exhibiting an output resistance, around the quiescent point, of 2.5 . Operate and at and V. The technology utilized is specified to have , and VDD =VSS = 2.5V. (a) Specify (W/L) for each of and (b) Specify the required value of (c) What is the expected error in the stage gain? (d) In the quiescent state, what dc voltage must appear at the output of each of the error amplifiers? (e) At what value of positive will be supplying all the load current? Repeat for negative and supplying all the load current. (f) What is the linear range of

A particular transistor having a thermal resistance JA = 2C/W is operating at an ambient temperature of 30C with a collectoremitter voltage of 20 V. If long life requires a maximum junction temperature of 130C, what is the corresponding device power rating? What is the greatest average collector current that should be considered?

A particular transistor has a power rating at 25C of 200 mW, and a maximum junction temperature of 150C. What is its thermal resistance? What is its power rating when operated at an ambient temperature of 70C? What is its junction temperature when dissipating 100 mW at an ambient temperature of 50C?

A power transistor operating at an ambient temperature of 50C, and an average emitter current of 3A, dissipates 30 W. If the thermal resistance of the transistor is known to be less than 3C/W, what is the greatest junction temperature you would expect? If the transistor VBE measured using a pulsed emitter current of 3 A at a junction temperature of 25C is 0.80V, what average VBE would you expect under normal operating conditions? (Use a temperature coefficient of 2 mV/C.)

For a particular application of the transistor specified in Example 11.7, extreme reliability is essential. To improve reliability, the maximum junction temperature is to be limited to 100C. What are the consequences of this decision for the conditions specified?

A power transistor is specified to have a maximum junction temperature of 130C. When the device is operated at this junction temperature with a heat sink, the case temperature is found to be 90C. The case is attached to the heat sink with a bond having a thermal resistance CS = 0.5C/W and the thermal resistance of the heat sink SA = 0.1C/W. If the ambient temperature is 30C what is the power being dissipated in the device? What is the thermal resistance of the device, JC, from junction to case?

A power transistor for which TJmax = 180C can dissipate 50 W at a case temperature of 50C. If it is connected to a heat sink using an insulating washer for which the thermal resistance is 0.6C/W, what heat-sink temperature is necessary to ensure safe operation at 30 W? For an ambient temperature of 39C, what heat-sink thermal resistance is required? If, for a particular extruded-aluminum-finned heat sink, the thermal resistance in still air is 4.5C/W per centimeter of length, how long a heat sink is needed?

Use the results given in the answer to Exercise 11.14 to determine the input current of the circuit in Fig. 11.30 for vI = 0 and 10 V with infinite and 100- loads.

For the circuit in Fig 11.30 when operated near and fed with a signal source having zero resistance, show that the output resistance is given by Assume that the top and bottom halves of the circuit are perfectly matched.

Consider the circuit of Fig. 11.30 in which Q1 and Q2 are matched, and Q3 and Q4 are matched but have three times the junction area of the others. For VCC = 10 V, find values for resistors R1 through R4 which allow for a base current of at least 10 mA in Q3 and Q4 at vI = +5 V (when a load demands it) with at most a 2-to-1 variation in currents in Q1 and Q2, and a no-load quiescent current of 40 mA in Q3 and Q4; , and For input voltages around 0 V, estimate the output resistance of the overall follower driven by a source having zero resistance. For an input voltage of +1 V and a load resistance of 2 , what output voltage results? Q1 and Q2 have of 0.7 V at a current of 10 mA.

Figure P11.39 shows a variant of the class AB circuit of Fig. 11.30. Assume that all four transistors are matched and have (a) For , find the quiescent current in and , the input current , and the output voltage (b) Since the circuit has perfect symmetry, the small-signal performance around can be determined by considering either the top or bottom half of the circuit only. In this case, the load on the half-circuit must be the input resistance found is and the output resistance found is Using this approach, find , , and (assuming that the circuit is fed with a zero-resistance source).

For the Darlington configuration shown in Fig. 11.31, show that for and : (a) The equivalent composite transistor has (b) If the composite transistor is operated at a current , then will be operating at a collector current approximately equal to and will be operating at a collector current approximately equal to . (c) The composite transistor has a , where is the saturation current of each of and (d) The composite transistor has an equivalent (e) The composite transistor has an equivalent

For the circuit in Fig. P11.41 in which the transistors have V and (a) Find the dc collector current for each of and (b) Find the small-signal current that results from an input signal , and hence find the voltage gain (c) Find the input resistance

The BJTs in the circuit of Fig. P11.42 have P = 10, N = 100, , and (a) Find the dc collector current of each transistor and the value of VC. (b) Replacing each BJT with its hybrid model, show that (c) Find the values of

Consider the compound-transistor class AB output stage shown in Fig. 11.33 in which Q2 and Q4 are matched transistors with VBE = 0.7 V at 10 mA and = 100, Q1 and Q5 have VBE = 0.7 V at 1-mA currents and = 100, and Q3 has VEB = 0.7 V at a 1-mA current and = 10. Design the circuit for a quiescent current of 2 mA in Q2 and Q4, IBIAS that is 100 times the standby base current in Q1, and a current in Q5 that is nine times that in the associated resistors. Find the values of the input voltage required to produce outputs of 10 V for a 1-k load. Use VCC of 15 V.

Repeat Exercise 11.16 for a design variation in which transistor Q5 is increased in size by a factor of 10, all other conditions remaining the same.

Repeat Exercise 11.16 for a design in which the limiting output current and normal peak current are 50 mA and 33.3 mA, respectively.

The circuit shown in Fig. P11.46 operates in a manner analogous to that in Fig. 11.35 to limit the output current from Q3 in the event of a short circuit or other mishap. It has the advantage that the current-sensing resistor R does not appear directly at the output. Find the value of R that causes Q5 to turn on and absorb all of IBIAS = 2 mA, when the current being sourced reaches 150 mA. For Q5, IS = 1014 A. If the normal peak output current is 100 mA, find the voltage drop across R and the collector current in Q5.

Consider the thermal shutdown circuit shown in Fig. 11.35. At 25C, Z1 is a 6.8-V zener diode with a TC of 2 mV/ C, and Q1 and Q2 are BJTs that display VBE of 0.7 V at a current of 100 A and have a TC of 2 mV/C. Design the circuit so that at 125C, a current of 100 A flows in each of Q1 and Q2. What is the current in Q2 at 25C?

In the power-amplifier circuit of Fig. 11.36 two resistors are important in controlling the overall voltage gain. Which are they? Which controls the gain alone? Which affects both the dc output level and the gain? A new design is being considered in which the output dc level is approximately (rather than approximately ) with a gain of 50 (as before). What changes are needed?

Consider the front end of the circuit in Fig. 11.36. For VS = 20 V, calculate approximate values for the bias currents in Q1 through Q6. Assume npn = 100, pnp = 20, and Also find the dc voltage at the output.

It is required to use the LM380 power amplifier to drive an 8- loudspeaker while limiting the maximum possible device dissipation to 1.5 W. Use the graph of Fig. 11.38 to determine the maximum possible power-supply voltage that can be used. (Use only the given graphs; do not interpolate.) If the maximum allowed THD is to be 3%, what is the maximum possible load power? To deliver this power totheload what peak-to-peak output sinusoidal voltage is required?

Consider the power-op-amp output stage shown in Fig. 11.39. Using a 15-V supply, provide a design that provides an output of 11 V or more, with currents up to 20mA provided primarily by Q3 and Q4 with a 10% contribution by Q5 and Q6, and peak output currents of 1 A at full output (+11 V). As the basis of an initial design, use = 50 and for all devices at all currents. Also use R5 = R6 = 0.

For the circuit in Fig. P11.52, assuming all transistors to have large , show that [This voltageto-current converter is an application of a versatile circuit building block known as the current conveyor; see Sedra and Roberts (1990)]. For = 100, by what approximate percentage is iO actually lower than this ideal value?

For the bridge amplifier of Fig. 11.40, let R1 = R3 = 10 k. Find R2 and R4 to obtain an overall gain of 10.

An alternative bridge amplifier configuration, with high input resistance, is shown in Fig. P11.54. (Note the similarity of this circuit to the front end of the instrumentation amplifier circuit shown in Fig. 2.20b.) What is the gain For op amps (using 15-V supplies) that limit at 13V, what is the largest sine wave you can provide across RL? Using 1 k as the smallest resistor, find resistor values that make Make sure that the signals at the outputs of the two amplifiers are complementary.

Consider the design of the class AB amplifier of Fig. 11.44 under the following conditions: Cox = 200 is high, IQN = IQP = IR = 10 mA, IBIAS = 100 A, R2 = R4, the temperature coefficient of VBE = 2 mV/C, and the temperature coefficient of Vt = 3 mV/C in the low-current region. Find the values of R, R1, R2, R3, and R4. Assume Q6, QP, and QN to be thermally coupled. (RG, used to suppress parisitic oscillation at high frequency, is usually 100 or so.)