For the circuit in Fig. P2.16, assuming an ideal op amp,

What is the minimum number of pins required for a socalled dual-op-amp IC package, one containing two op amps? What is the number of pins required for a so-called quad-op-amp package, one containing four op-amps?

The circuit of Fig. P2.2 uses an op amp that is ideal except for having a finite gain A. Measurements indicate vO = 4.0 V when vI = 2.0 V. What is the op-amp gain A?

Measurement of a circuit incorporating what is thought to be an ideal op amp shows the voltage at the op-amp output to be 2.000 V and that at the negative input to be 1.000 V. For the amplifier to be ideal, what would you expect the voltage at the positive input to be? If the measured voltage at the positive input is 1.010 V, what is likely to be the actual gain of the amplifier?

A set of experiments is run on an op amp that is ideal except for having a finite gain A. The results are tabulated below. Are the results consistent? If not, are they reasonable, in view of the possibility of experimental error? What do they show the gain to be? Using this value, predict values of the measurements that were accidentally omitted (the blank entries).

Refer to Exercise 2.3. This problem explores an alternative internal structure for the op amp. In particular, we wish to model the internal structure of a particular op amp using two transconductance amplifiers and one transresistance amplifier. Suggest an appropriate topology. For equal transconductances Gm and a transresistance Rm, find an expression for the open-loop gain A. For Gm = 10 mA/V and Rm = 2  106 , what value of A results?

The two wires leading from the output terminals of a transducer pick up an interference signal that is a 60-Hz, 1V sinusoid. The output signal of the transducer is sinusoidal of 10-mV amplitude and 1000-Hz frequency. Give expressions for vcm, vd, and the total signal between each wire and the system ground.

Nonideal (i.e., real) operational amplifiers respond to both the differential and common-mode components of their input signals (refer to Fig. 2.4 for signal representation). Thus the output voltage of the op amp can be expressed as where Ad is the differential gain (referred to simply as A in the text) and Acm is the common-mode gain (assumed to be zero in the text). The op amps effectiveness in rejecting common-mode signals is measured by its CMRR, defined as Consider an op amp whose internal structure is of the type shown in Fig. E2.3 except for a mismatch Gm between the transconductances of the two channels; that is, Find expressions for Ad, Acm, and CMRR. If Ad is 80 dB and the two transconductances are matched to within 0.1% of each other, calculate Acm and CMRR.

Assuming ideal op amps, find the voltage gain and input resistance Rin of each of the circuits in Fig. P2.8.

A particular inverting circuit uses an ideal op amp and two 10-k resistors. What closed-loop gain would you expect? If a dc voltage of +1.00 V is applied at the input, what output result? If the 10-k resistors are said to be 1% resistors, having values somewhere in the range (1 0.01) times the nominal value, what range of outputs would you expect to actually measure for an input of precisely 1.00 V?

You are provided with an ideal op amp and three 10k resistors. Using series and parallel resistor combinations, how many different inverting-amplifier circuit topologies are possible? What is the largest (noninfinite) available voltage gain? What is the smallest (nonzero) available gain? What are the input resistances in these two cases?

For ideal op amps operating with the following feedback networks in the inverting configuration, what closedloop gain results?

Given an ideal op amp, what are the values of the resistors R1 and R2 to be used to design amplifiers with the closed-loop gains listed below? In your designs, use at least one 10-k resistor and another equal or larger resistor. (a) 1 V/V (b) 2 V/V (c) 0.5 V/V (d) 100 V/V

Design an inverting op-amp circuit for which the gain is 4 V/V and the total resistance used is 100 k.

Using the circuit of Fig. 2.5 and assuming an ideal op amp, design an inverting amplifier with a gain of 26 dB having the largest possible input resistance under the constraint of having to use resistors no larger than 1 M. What is the input resistance of your design?

An ideal op amp is connected as shown in Fig. 2.5 with R1 = 10 k and R2 = 100 k. A symmetrical squarewave signal with levels of 0 V and 1 V is applied at the input. Sketch and clearly label the waveform of the resulting output voltage. What is its average value? What is its highest value? What is its lowest value?

For the circuit in Fig. P2.16, assuming an ideal op amp, find the currents through all branches and the voltages at all nodes. Since the current supplied by the op amp is greater than the current drawn from the input signal source, where does the additional current come from?

An inverting op-amp circuit is fabricated with the resistors R1 and R2 having x% tolerance (i.e., the value of each resistance can deviate from the nominal value by as much as x%). What is the tolerance on the realized closedloop gain? Assume the op amp to be ideal. If the nominal closed-loop gain is 100 V/V and x = 1, what is the range of gain values expected from such a circuit?

An ideal op amp with 5-k and 15-k resistors is used to create a +5-V supply from a 15-V reference. Sketch the circuit. What are the voltages at the ends of the 5k resistor? If these resistors are so-called 1% resistors, whose actual values are the range bounded by the nominal value 1%, what are the limits of the output voltage produced? If the 15-V supply can also vary by 1%, what is the range of the output voltages that might be found?

An inverting op-amp circuit for which the required gain is 50 V/V uses an op amp whose open-loop gain is only 300V/V. If the larger resistor used is 100 k, to what must the smaller be adjusted? With what resistor must a 2-k resistor connected to the input be shunted to achieve this goal? (Note that a resistor Ra is said to be shunted by resistor Rb when Rb is placed in parallel with Ra.)

(a) Design an inverting amplifier with a closedloop gain of 100 V/V and an input resistance of 1 k. (b) If the op amp is known to have an open-loop gain of 2000 V/V, what do you expect the closed-loop gain of your circuit to be (assuming the resistors have precise values)? (c) Give the value of a resistor you can place in parallel (shunt) with R1 to restore the closed-loop gain to its nominal value. Use the closest standard 1% resistor value (see Appendix H).

An op amp with an open-loop gain of 2000 V/V is used in the inverting configuration. If in this application the output voltage ranges from 10 V to +10 V, what is the maximum voltage by which the virtual ground node departs from its ideal value?

The circuit in Fig. P2.22 is frequently used to provide an output voltage vo proportional to an input signal current ii.Derive expressions for the transresistance and the input resistance for the following cases: (a) A is infinite. (b) A is finite.

Show that for the inverting amplifier if the op-amp gain is A, the input resistance is given by

For an inverting amplifier with nominal closed-loop gain , find the minimum value that the op-amp openloop gain A must have (in terms of ) so that the gain error is limited to 0.1%, 1%, and 10%. In each case find the value of a resistor RIa such that when it is placed in shunt with Ri, the gain is restored to its nominal value.

Figure P2.25 shows an op amp that is ideal except for having a finite open-loop gain and is used to realize an inverting amplifier whose gain has a nominal magnitude To compensate for the gain reduction due to the finite A, a resistor Rc is shunted across R1. Show that perfect compensation is achieved when Rc is selected according to

(a) Use Eq. (2.5) to obtain the amplifier open-loop gain A required to realize a specified closed-loop gain within a specified gain error , (b) Design an inverting amplifer for a nominal closed-loop gain of 100, an input resistance of 2 k, and a gain error of 10%. Specify R1, R2, and the minimum A required.

(a) Use Eq. (2.5) to show that a reduction in the opamp gain A gives rise to a reduction in the magnitude of the closed-loop gain G with and related by (b) If in a closed-loop amplifier with a nominal gain (i.e, ) of 100, A decreases by 50%, what is the minimum nominal A required to limit the percentage change in to 0.5%?

Consider the circuit in Fig. 2.8 with R1 = R2 = R4 = 1M, and assume the op amp to be ideal. Find values for R3 to obtain the following gains: (a) 200 V/V (b) 20 V/V (c) 2 V/V

An inverting op-amp circuit using an ideal op amp must be designed to have a gain of 1000 V/V using resistors no larger than 100 k. (a) For the simple two-resistor circuit, what input resistance would result? (b) If the circuit in Fig. 2.8 is used with three resistors of maximum value, what input resistance results? What is the value of the smallest resistor needed?

The inverting circuit with the T network in the feedback is redrawn in Fig. P2.30 in a way that emphasizes the observation that R2 and R3 in effect are in parallel (because the ideal op amp forces a virtual ground at the inverting input terminal). Use this observation to derive an expression for the gain by first finding and For the latter use the voltage-divider rule applied to R4 and (R2 || R3).

The circuit in Fig. P2.31 can be considered to be an extension of the circuit in Fig. 2.8. (a) Find the resistances looking into node 1, R1; node 2, R2; node 3, R3; and node 4, R4. (b) Find the currents I1, I2, I3, and I4, in terms of the input current I. (c) Find the voltages at nodes 1, 2, 3, and 4, that is, V1, V2, V3, and V4 in terms of (IR).

The circuit in Fig. P2.32 utilizes an ideal op amp. (a) Find I1, I2, I3, IL, and Vx. (b) If VO is not to be lower than 13 V, find the maximum allowed value for RL. (c) If RL is varied in the range 100 to 1 k, what is the corresponding change in IL and in VO?

Use the circuit in Fig. P2.32 as an inspiration to design a circuit that supplies a constant current I of 3.1 mA to a variable resistance RL. Assume the availability of a 1.5 V battery and design so that the current drawn from the battery is 0.1 mA. For the smallest resistance in the circuit, use 500 . If the op amp saturates at 12 V, what is the maximum value that RL can have while the current-source supplying it operates properly?

Assuming the op amp to be ideal, it is required to design the circuit shown in Fig. P2.34 to implement a current amplifier with gain "(a) Find the required value for R. (b) What are the input and the output resistance of this current amplifier?(c) If RL = 1 k and the op amp operates in an ideal manner as long as vO is in the range 12 V, what range of iI is possible? (d) If the amplifier is fed with a current source having a current of 0.2 mA and a source resistance of 10 k, find iL. "

Design the circuit shown in Fig. P2.35 to have an input resistance of 100 k and a gain that can be varied from 1 V/V to 10 V/V using the 10-k potentiometer R4. What voltage gain results when the potentiometer is set exactly at its middle value?

A weighted summer circuit using an ideal op amp has three inputs using 100-k resistors and a feedback resistor of 50 k. A signal v1 is connected to two of the inputs while a signalv2 is connected to the third. Express vO in terms of v1 and v2. If v1 = 2 V and v2 = 2 V, what is vO?

Design an op amp circuit to provide an output Choose relatively low values of resistors but ones for which the input current (from each input signal source) does not exceed 0.1 mA for 1-V input signals.

Use the scheme illustrated in Fig. 2.10 to design an op-amp circuit with inputs v1, v2, and v3, whose output is vO = (2v1 + 4v2 + 8v3) using small resistors but no smaller than 10 k.

An ideal op amp is connected in the weighted summer configuration of Fig. 2.10. The feedback resistor Rf = 10 k, and six 10-k resistors are connected to the inverting input terminal of the op amp. Show, by sketching the various circuit configurations, how this basic circuit can be used to implement the following functions: In each case find the input resistance seen by each of the signal sources supplying v1, v2, v3, and v4. Suggest at least two additional summing functions that you can realize with this circuit. How would you realize a summing coefficient that is 0.5?

Give a circuit, complete with component values, for a weighted summer that shifts the dc level of a sine-wave signal of 3 sin( t) V from zero to 3 V. Assume that in addition to the sine-wave signal you have a dc reference voltage of 1.5V available. Sketch the output signal waveform.

Use two ideal op amps and resistors to implement the summing function

In an instrumentation system, there is a need to take the difference between two signals, one of v1 = 2 sin(2 60t) + 0.01 sin(2 1000t) volts and another of v2 = 2 sin(2 60t) 0.01 sin(2 1000t) volts. Draw a circuit that finds the required difference using two op amps and mainly 100-k resistors. Since it is desirable to amplify the 1000-Hz component in the process, arrange to provide an overall gain of 100 as well. The op amps available are ideal except that their output voltage swing is limited to 10 V.

Figure P2.43 shows a circuit for a digital-to-analog converter (DAC). The circuit accepts a 4-bit input binary word a3a2a1a0, where a0, a1, a2, and a3 take the values of 0 or 1, and it provides an analog output voltage vO proportional to the value of the digital input. Each of the bits of the input word controls the correspondingly numbered switch. For instance, if a2 is 0 then switch S2 connects the 20-k resistor to ground, while if a2 is 1 then S2 connects the 20-k resistor to the +5-V power supply. Show that vO is given by where Rf is in kilohms. Find the value of Rf so that vO ranges from 0 to 12 volts.

Given an ideal op amp to implement designs for the following closed-loop gains, what values of resistors (R1, R2) should be used? Where possible, use at least one 10-k resistor as the smallest resistor in your design. (a) +1 V/V (b) +2 V/V (c) +11 V/V (d) +100 V/V

Design a circuit based on the topology of the noninverting amplifier to obtain a gain of +1.5 V/V, using only 10-k resistors. Note that there are two possibilities. Which of these can be easily converted to have a gain of either +1.0 V/V or +2.0 V/V simply by short-circuiting a single resistor in each case?

Figure P2.46 shows a circuit for an analog voltmeter of very high input resistance that uses an inexpensive moving-coil meter. The voltmeter measures the voltage V applied between the op amps positive-input terminal and ground. Assuming that the moving coil produces full-scale deflection when the current passing through it is 100 A, find the value of R such that full-scale reading is obtained when V is +10 V. Does the meter resistance shown affect the voltmeter calibration?

(a) Use superposition to show that the output of the circuit in Fig. P2.47 is given by where RN = RN1||RN2|| . . . ||RNn and RP = RP1||RP2|| . . . ||RPn||RP0 (b) Design a circuit to obtain The smallest resistor used should be 10 k

Design a circuit, using one ideal op amp, whose output is vO = vI1 + 3vI2 2(vI3 + 3vI4). (Hint: Use a structure similar to that shown in general form in Fig. P2.47.)

Derive an expression for the voltage gain, of the circuit in Fig. P2.49.

For the circuit in Fig. P2.50, use superposition to find vO in terms of the input voltages v1 and v2. Assume an ideal op amp. For find

The circuit shown in Fig. P2.51 utilizes a 10-k potentiometer to realize an adjustable-gain amplifier. Derive an expression for the gain as a function of the potentiometer setting x. Assume the op amp to be ideal. What is the range of gains obtained? Show how to add a fixed resistor so that the gain range can be 1 to 11 V/V. What should the resistor value be?

Given the availability of resistors of value 1 k and 10 k only, design a circuit based on the noninverting configuration to realize a gain of +10 V/V.

It is required to connect a 10-V source with a source resistance of 100 k to a 1-k load. Find the voltage that will appear across the load if:(a) The source is connected directly to the load. (b) A unity-gain op-amp buffer is inserted between the source and the load.In each case find the load current and the current supplied by the source. Where does the load current come from in case (b)?

Derive an expression for the gain of the voltage follower of Fig. 2.14, assuming the op amp to be ideal except for having a finite gain A. Calculate the value of the closed-loop gain for A = 1000, 100, and 10. In each case find the percentage error in gain magnitude from the nominal value of unity.

Complete the following table for feedback amplifiers created using one ideal op amp. Note that Rin signifies input resistance and R1 and R2 are feedback-network resistors as labelled in the inverting and noninverting configurations.

A noninverting op-amp circuit with nominal gain of 10 V/V uses an op amp with open-loop gain of 50 V/V and a lowest-value resistor of 10 k. What closed-loop gain actually results? With what value resistor can which resistor be shunted to achieve the nominal gain? If in the manufacturing process, an op amp of gain 100 V/V were used, what closed-loop gain would result in each case (the uncompensated one, and the compensated one)?

Use Eq. (2.11) to show that if the reduction in the closed-loop gain G from the nominal value is to be kept less than x% of G0, then the open-loop gain of the op amp must exceed G0 by at least a factor F = Find the required F for x = 0.01, 0.1, 1, and 10. Utilize these results to find for each value of x the minimum required open-loop gain to obtain closed-loop gains of 1, 10, 102, 103, and 104 V/V.

For each of the following combinations of op-amp open-loop gain A and nominal closed-loop gain G0, calculate the actual closed-loop gain G that is achieved. Also, calculate the percentage by which falls short of the nominal gain magnitude

Figure P2.59 shows a circuit that provides an output voltage vO whose value can be varied by turning the wiper of the 100-k potentiometer. Find the range over which vO can be varied. If the potentiometer is a 20-turn device, find the change in vO corresponding to each turn of the pot.

Find the voltage gain for the difference amplifier of Fig. 2.16 for the case R1 = R3 = 10 k and R2 = R4 = 100 k. What is the differential input resistance Rid? If the two key resistance ratios and are different from each other by 1%, what do you expect the common-mode gain Acm to be? Also, find the CMRR in this case. Neglect the effect of the ratio mismatch on the value of Ad.

Using the difference amplifier configuration of Fig. 2.16 and assuming an ideal op amp, design the circuit to provide the following differential gains. In each case, the differential input resistance should be 20 k. (a) 1 V/V (b) 2 V/V (c) 100 V/V (d) 0.5 V/V

For the circuit shown in Fig. P2.62, express vO as a function of v1 and v2. What is the input resistance seen by v1 alone? By v2 alone? By a source connected between the two input terminals? By a source connected to both input terminals simultaneously?

Consider the difference amplifier of Fig. 2.16 with the two input terminals connected together to an input common-mode signal source. For show that the input common-mode resistance is

Consider the circuit of Fig. 2.16, and let each of the vI1 and vI2 signal sources have a series resistance Rs. What condition must apply in addition to the condition in Eq. (2.15) in order for the amplifier to function as an ideal difference amplifier?

For the difference amplifier shown in Fig. P2.62, let all the resistors be 10 k x%. Find an expression for the worst-case common-mode gain that results. Evaluate this for x= 0.1, 1, and 5. Also, evaluate the resulting CMRR in each case. Neglect the effect of resistor tolerances on Ad.

For the difference amplifier of Fig. 2.16, show that if each resistor has a tolerance of 100 % (i.e., for, say, a 5% resistor, = 0.05) then the worst-case CMRR is given approximately by where K is the nominal (ideal) value of the ratios and Calculate the value of worst-case CMRR for an amplifier designed to have a differential gain of ideally 100 V/V, assuming that the op amp is ideal and that 1% resistors are used.

Design the difference amplifier circuit of Fig. 2.16 to realize a differential gain of 100, a differential input resistance of 20 k, and a minimum CMRR of 80 dB. Assume the op amp to be ideal. Specify both the resistor values and their required tolerance (e.g., better than x%).

(a) Find Ad and Acm for the difference amplifier circuit shown in Fig. P2.68. (b) If the op amp is specified to operate properly as long as the common-mode voltage at its positive and negative inputs falls in the range 2.5 V, what is the corresponding limitation on the range of the input common-mode signal vIcm? (This is known as the common-mode range of the differential amplifier.) (c) The circuit is modified by connecting a 10-k resistor between node A and ground, and another 10-k resistor between node B and ground. What will now be the values of Ad, Acm, and the input common-mode range?

To obtain a high-gain, high-input-resistance difference amplifier, the circuit in Fig. P2.69 employs positive feedback, in addition to the negative feedback provided by the resistor R connected from the output to the negative input of the op amp. Specifically, a voltage divider (R5, R6) connected across the output feeds a fraction of the output, that is, a voltage vO, back to the positive-input terminal of the op ampthrough a resistor R. Assume that R5 and R6 are much smaller than R so that the current through R is much lower than the current in the voltage divider, with the result that Show that the differential gain is given by (Hint: Use superposition.) Design the circuit to obtain a differential gain of 10 V/V and differential input resistance of 2 M. Select values for R, R5, and R6, such that

Figure P2.70 shows a modified version of the difference amplifier. The modified circuit includes a resistor RG, which can be used to vary the gain. Show that the differential voltage gain is given by (Hint: The virtual short circuit at the op-amp input causes the current through the R1 resistors to be

The circuit shown in Fig. P2.71 is a representation of a versatile, commercially available IC, the INA105, manufactured by Burr-Brown and known as a differential amplifier module. It consists of an op amp and precision, lasertrimmed, metal-film resistors. The circuit can be configured for a variety of applications by the appropriate connection of terminals A, B, C, D, and O. (a) Show how the circuit can be used to implement a difference amplifier of unity gain. (b) Show how the circuit can be used to implement single-ended amplifiers with gains: (i) 1 V/V (ii) +1 V/V (iii) +2 V/V (iv) +1/2 V/V Avoid leaving a terminal open-circuited, for such a terminal may act as an antenna, picking up interference and noise through capacitive coupling. Rather, find a convenient node to connect such a terminal in a redundant way. When more than one circuit implementation is possible, comment on the relative merits of each, taking into account such considerations as dependence on component matching and input resistance.

Consider the instrumentation amplifier of Fig. 2.20(b) with a common-mode input voltage of +2 V (dc) and a differential input signal of 80-mV peak sine wave. Let 2R1 = 2k, R2 = 50 k, R3 = R4 = 10 k. Find the voltage at every node in the circuit.

(a) Consider the instrumentation amplifier circuit of Fig. 2.20(a). If the op amps are ideal except that their outputs saturate at 14 V, in the manner shown in Fig. 1.14, find the maximum allowed input common-mode signal for the case R1 = 1 k and R2 = 100 k. (b) Repeat (a) for the circuit in Fig. 2.20(b), and comment on the difference between the two circuits.

(a) Expressing vI1 and vI2 in terms of differential and common-mode components, find vO1 and vO2 in the circuit in Fig. 2.20(a) and hence find their differential component vO2 vO1 and their common-mode component Now find the differential gain and the commonmode gain of the first stage of this instrumentation amplifier and hence the CMRR. (b) Repeat for the circuit in Fig. 2.20(b), and comment on the difference between the two circuits.

For an instrumentation amplifier of the type shown in Fig. 2.20(b), a designer proposes to make R2 = R3 = R4 = 100 k, and 2R1 = 10 k. For ideal components, what difference-mode gain, common-mode gain, and CMRR result? Reevaluate the worst-case values for these for the situation in which all resistors are specified as 1% units. Repeat the latter analysis for the case in which 2R1 is reduced to 1 k. What do you conclude about the effect of the gain of the first stage on CMRR? (Hint: Eq. (2.19) can be used to evaluate Acm of the second stage.)

Design the instrumentation-amplifier circuit of Fig. 2.20(b) to realize a differential gain, variable in the range 1 to 100, utilizing a 100-k pot as variable resistor. (Hint: Design the second stage for a gain of 0.5.)

The circuit shown in Fig. P2.77 is intended to supply a voltage to floating loads (those for which both terminals are ungrounded) while making greatest possible use of the available power supply. (a) Assuming ideal op amps, sketch the voltage waveforms at nodes B and C for a 1-V peak-to-peak sine wave applied at A. Also sketch vO. (b) What is the voltage gain (c) Assuming that the op amps operate from 15-V power supplies and that their output saturates at 14 V (in the manner shown in Fig. 1.14), what is the largest sine-wave output that can be accommodated? Specify both its peak-topeak and rms values.

The two circuits in Fig. P2.78 are intended to function as voltage-to-current converters; that is, they supply the load impedance ZL with a current proportional to vI and independent of the value of ZL. Show that this is indeed the case, and find for each circuit iO as a function of vI. Comment on the differences between the two circuits.

A Miller integrator incorporates an ideal op amp, a resistor R of 100 k, and a capacitor C of 1 nF. A sine-wave signal is applied to its input. (a) At what frequency (in Hz) are the input and output signals equal in amplitude? (b) At that frequency, how does the phase of the output sine wave relate to that of the input? (c) If the frequency is lowered by a factor of 10 from that found in (a), by what factor does the output voltage change, and in what direction (smaller or larger)? (d) What is the phase relation between the input and output in situation (c)?

Design a Miller integrator with a time constant of 0.1 s and an input resistance of 100 k. A dc voltage of 1 volt is applied at the input at time 0, at which moment vO = 10 V. How long does it take the output to reach 0 V? +10 V?

An op-amp-based inverting integrator is measured at 1 kHz to have a voltage gain of 100 V/V. At what frequency is its gain reduced to 1 V/V? What is the integrator time constant?

Design a Miller integrator that has a unity-gain frequency of 1 krad/s and an input resistance of 100 k. Sketch the output you would expect for the situation in which, with output initially at 0 V, a 2-V, 2-ms pulse is applied to the input. Characterize the output that results when a sine wave 2 sin 1000t is applied to the input.

Design a Miller integrator whose input resistance is 20 k and unity-gain frequency is 10 kHz. What components are needed? For long-term stability, a feedback resistor is introduced across the capacitor, limits the dc gain to 40 dB. What is its value? What is the associated lower 3-dB frequency? Sketch and label the output that results with a 0.1-ms, 1-V positive-input pulse (initially at 0 V) with (a) no dc stabilization (but with the output initially at 0 V) and (b) the feedback resistor connected.

A Miller integrator whose input and output voltages are initially zero and whose time constant is 1 ms is driven by the signal shown in Fig. P2.84. Sketch and label the output waveform that results. Indicate what happens if the input levels are 2 V, with the time constant the same (1 ms) and with the time constant raised to 2 ms.

Consider a Miller integrator having a time constant of 1 ms and an output that is initially zero, when fed with a string of pulses of 10-s duration and 1-V amplitude rising from 0 V (see Fig. P2.85). Sketch and label the output wave form resulting. How many pulses are required for an output voltage change of 1 V?

Figure P2.86 shows a circuit that performs a lowpass STC function. Such a circuit is known as a first-order, low-pass active filter. Derive the transfer function and show that the dc gain is and the 3-dB frequency Design the circuit to obtain an input resistance of 10 k, a dc gain of 20 dB, and a 3-dB frequency of 10 kHz. At what frequency does the magnitude of the transfer function reduce to unity?

Show that a Miller integrator implemented with an op amp with open-loop gain A0 has a low-pass STC transfer function. What is the pole frequency of the STC function? How does this compare with the pole frequency of the ideal integrator? If an ideal Miller integrator is fed with a 1-V pulse signal with a width T = CR, what will the output voltage be at t = T? Assume that at t = 0, vO = 0. Repeat for an integrator with an op amp having A0 = 1000.

A differentiator utilizes an ideal op amp, a 10-k resistor, and a 0.01-F capacitor. What is the frequency f0 (inHz) at which its input and output sine-wave signals have equal magnitude? What is the output signal for a 1-V peak-to-peak sine-wave input with frequency equal to 10f0?

An op-amp differentiator with 1-ms time constant is driven by the rate-controlled step shown in Fig. P2.89. Assuming vO to be zero initially, sketch and label its waveform.

An op-amp differentiator, employing the circuit shown in Fig. 2.27(a), has R = 10 k and C = 0.1 F. When a triangle wave of 1-V peak amplitude at 1 kHz is applied to the input, what form of output results? What is its frequency? What is its peak amplitude? What is its average value? What value of R is needed to cause the output to have a 10-V peak amplitude?

Use an ideal op amp to design a differentiation circuit for which the time constant is 103 s using a 10-nF capacitor. What are the gains and phase shifts found for this circuit at one-tenth and 10 times the unity-gain frequency? A series input resistor is added to limit the gain magnitude at high frequencies to 100 V/V. What is the associated 3-dB frequency? What gain and phase shift result at 10 times the unity-gain frequency?

Figure P2.92 shows a circuit that performs the high-pass, single-time-constant function. Such a circuit is known as a first-order high-pass active filter. Derive the transfer function and show that the high-frequency gain is and the 3-dB frequency Design the circuit to obtain a high-frequency input resistance of 10 k, a high-frequency gain of 40 dB, and a 3-dB frequency of 500 Hz. At what frequency does the magnitude of the transfer function reduce to unity?

Derive the transfer function of the circuit in Fig. P2.93 (for an ideal op amp) and show that it can be written in the form where and Assuming that the circuit is designed such that 2 1, find approximate expressions for the transfer function in the following frequency regions: (a)  1 (b) 1   2 (c) 2 Use these approximations to sketch a Bode plot for the magnitude response. Observe that the circuit performs as an amplifier whose gain rolls off at the low-frequency end in the manner of a high-pass STC network, and at the highfrequency end in the manner of a low-pass STC network. Design the circuit to provide a gain of 40 dB in the middle frequency range, a low-frequency 3-dB point at 100 Hz, a high-frequency 3-dB point at 100 kHz, and an input resistance (at

An op amp wired in the inverting configuration with the input grounded, having R2 = 100 k and R1 = 1 k, has an output dc voltage of 0.4 V. If the input bias current is known to be very small, find the input offset voltage.

A noninverting amplifier with a gain of 200 uses an op amp having an input offset voltage of 2 mV. Find the output when the input is 0.01 sin

A noninverting amplifier with a closed-loop gain of 1000 is designed using an op amp having an input offset voltage of 5 mV and output saturation levels of 13 V. What is the maximum amplitude of the sine wave that can be applied at the input without the output clipping? If the amplifier is capacitively coupled in the manner indicated in Fig. 2.36, what would the maximum possible amplitude be?

An op amp connected in a closed-loop inverting configuration having a gain of 1000 V/V and using relatively small-valued resistors is measured with input grounded to have a dc output voltage of 1.4 V. What is its input offset voltage? Prepare an offset-voltage-source sketch resembling that in Fig. 2.28. Be careful of polarities.

A particular inverting amplifier with nominal gain of 100 V/V uses an imperfect op amp in conjunction with 100-k and 10-M resistors. The output voltage is found to be +9.31 V when measured with the input open and +9.09 V with the input grounded.(a) What is the bias current of this amplifier? In what direction does it flow? (b) Estimate the value of the input offset voltage. (c) A 10-M resistor is connected between the positiveinput terminal and ground. With the input left floating (disconnected), the output dc voltage is measured to be 0.8 V. Estimate the input offset current.

A noninverting amplifier with a gain of +10 V/V using 100 k as the feedback resistor operates from a 5-k source. For an amplifier offset voltage of 0 mV, but with a bias current of 1 A and an offset current of 0.1 A, what range of outputs would you expect? Indicate where you would add an additional resistor to compensate for the bias currents. What does the range of possible outputs then become? A designer wishes to use this amplifier with a 15k source. In order to compensate for the bias current in this case, what resistor would you use? And where?

The circuit of Fig. 2.36 is used to create an accoupled noninverting amplifier with a gain of 200 V/V using resistors no larger than 100 k. What values of R1, R2, and R3 should be used? For a break frequency due to C1 at 100 Hz, and that due to C2 at 10 Hz, what values of C1 and C2 are needed?

Consider the difference amplifier circuit in Fig. 2.16. Let R1 = R3 = 10 k and R2 = R4 = 1 M. If the op amp has VOS = 4 mV, IB = 0.5 A, and IOS = 0.1 A, find the worstcase (largest) dc offset voltage at the output.

The circuit shown in Fig. P2.102 uses an op amp having a 4-mV offset. What is its output offset voltage? What does the output offset become with the input ac coupled through a capacitor C? If, instead, a large capacitor is placed in series with 1-k resistor, what does the output offset become?

Using offset-nulling facilities provided for the op amp, a closed-loop amplifier with gain of +1000 is adjusted at 25C to produce zero output with the input grounded. If the input offset-voltage drift of the op amp is specified to be 10V/C, what output would you expect at 0C and at 75C? While nothing can be said separately about the polarity of the output offset at either 0 or 75C, what would you expect their relative polarities to be?

An op amp is connected in a closed loop with gain of +100 utilizing a feedback resistor of 1 M. (a) If the input bias current is 100 nA, what output voltage results with the input grounded? (b) If the input offset voltage is 1 mV and the input bias current as in (a), what is the largest possible output that can be observed with the input grounded? (c) If bias-current compensation is used, what is the value of the required resistor? If the offset current is no more than one-tenth the bias current, what is the resulting output offset voltage (due to offset current alone)? (d) With bias-current compensation as in (c) in place what is the largest dc voltage at the output due to the combined effect of offset voltage and offset current?

An op amp intended for operation with a closedloop gain of 100 V/V uses resistors of 10 k and 1 M with a bias-current-compensation resistor R3. What should the value of R3 be? With input grounded, the output offset voltage is found to be +0.21 V. Estimate the input offset current assuming zero input offset voltage. If the input offset voltage can be as large as 1 mV of unknown polarity, what range of offset current is possible?

A Miller integrator with R = 10 k and C = 10 nF is implemented by using an op amp with VOS = 3 mV, IB = 0.1 A, and IOS = 10 nA. To provide a finite dc gain, a 1-M resistor is connected across the capacitor. (a) To compensate for the effect of IB, a resistor is connected in series with the positive-input terminal of the op amp. What should its value be? (b) With the resistor of (a) in place, find the worst-case dc output voltage of the integrator when the input is grounded.

The data in the following table apply to internally compensated op amps. Fill in the blank entries.

A measurement of the open-loop gain of an internally compensated op amp at very low frequencies shows it to be 92 dB; at 100 kHz, this shows it is 40 dB. Estimate values for A0, fb, and ft.

Measurements of the open-loop gain of a compensated op amp intended for high-frequency operation indicate that the gain is 5.1 103 at 100 kHz and 8.3 103 at 10 kHz. Estimate its 3-dB frequency, its unity-gain frequency, and its dc gain.

Measurements made on the internally compensated amplifiers listed below provide the dc gain and the frequency at which the gain has dropped by 20 dB. For each, what are the 3 dB and unity-gain frequencies? (a) 3 105 V/V and 6 102 Hz (b) 50 105 V/V and 10 Hz (c) 1500 V/V and 0.1 MHz (d) 100 V/V and 0.1 GHz (e) 25 V/mV and 25 kHz

An inverting amplifier with nominal gain of 20 V/V employs an op amp having a dc gain of 104 and a unity-gain frequency of 106 Hz. What is the 3-dB frequency f3dB of the closed-loop amplifier? What is its gain at 0.1 f3dB and at 10 f3dB?

A particular op amp, characterized by a gainbandwidth product of 10 MHz, is operated with a closed-loop gain of +100 V/V. What 3-dB bandwidth results? At what frequency does the closed-loop amplifier exhibit a 6 phase shift? A 84 phase shift?

Find the ft required for internally compensated op amps to be used in the implementation of closed-loop amplifiers with the following nominal dc gains and 3-dB bandwidths: (a) 100 V/V; 100 kHz (b) +100 V/V; 100 kHz (c) +2 V/V; 10 MHz (d) 2 V/V; 10 MHz (e) 1000 V/V; 20 kHz (f) +1 V/V; 1 MHz (g) 1 V/V; 1 MHz

A noninverting op-amp circuit with a gain of 96 V/V is found to have a 3-dB frequency of 8 kHz. For a particular system application, a bandwidth of 24 kHz is required. What is the highest gain available under these conditions?

Consider a unity-gain follower utilizing an internally compensated op amp with ft = 1 MHz. What is the 3-dB frequency of the follower? At what frequency is the gain of the follower 1% below its low-frequency magnitude? If the input to the follower is a 1-V step, find the 10% to 90% rise time of the output voltage. (Note: The step response of STC low-pass networks is discussed in Appendix E.)

It is required to design a noninverting amplifier with a dc gain of 10. When a step voltage of 100 mV is applied at the input, it is required that the output be within 1% of its final value of 1 V in at most 100 ns. What must the ft of the op amp be? (Note: The step response of STC lowpass networks is discussed in Appendix E.)

This problem illustrates the use of cascaded closed-loop amplifiers to obtain an overall bandwidth greater than can be achieved using a single-stage amplifier with the same overall gain. (a) Show that cascading two identical amplifier stages, each having a low-pass STC frequency response with a 3dB frequency f1, results in an overall amplifier with a 3dB frequency given by (b) It is required to design a noninverting amplifier with a dc gain of 40 dB utilizing a single internally compensated op amp with ft = 1 MHz. What is the 3-dB frequency obtained? (c) Redesign the amplifier of (b) by cascading two identical noninverting amplifiers each with a dc gain of 20 dB. What is the 3-dB frequency of the overall amplifier? Compare this to the value obtained in (b) above.

A designer, wanting to achieve a stable gain of 100 V/V at 5 MHz, considers her choice of amplifier topologies. What unity-gain frequency would a single operational amplifier require to satisfy her need? Unfortunately, the best available amplifier has an ft of 40 MHz. How many such amplifiers connected in a cascade of identical noninverting stages would she need to achieve her goal? What is the 3-dB frequency of each stage she can use? What is the overall 3-dB frequency?

Consider the use of an op amp with a unity-gain frequency ft in the realization of: (a) An inverting amplifier with dc gain of magnitude K. (b) A noninverting amplifier with a dc gain of K. In each case find the 3-dB frequency and the gain-bandwidth product (GBP |Gain| f3dB). Comment on the results.

Consider an inverting summer with two inputs V1 and V2 and with Vo = (V1 + 2V2). Find the 3-dB frequency of each of the gain functions and in terms of the op amp ft. (Hint: In each case, the other input to the summer can be set to zeroan application of superposition.)

A particular op amp using 15-V supplies operates linearly for outputs in the range 12 V to +12 V. If used in an inverting amplifier configuration of gain 100, what is the rms value of the largest possible sine wave that can be applied at the input without output clipping?

Consider an op amp connected in the inverting configuration to realize a closed-loop gain of 100 V/V utilizing resistors of 1 k and 100 k. A load resistance RL is connected from the output to ground, and a low-frequency sine-wave signal of peak amplitude Vp is applied to the input. Let the op amp be ideal except that its output voltage saturates at 10 V and its output current is limited to the range 20 mA. (a) For RL = 1 k, what is the maximum possible value of Vp while an undistorted output sinusoid is obtained? (b) Repeat (a) for RL = 100 . (c) If it is desired to obtain an output sinusoid of 10-V peak amplitude, what minimum value of RL is allowed?

An op amp having a slew rate of 10 V/s is to be used in the unity-gain follower configuration, with input pulses that rise from 0 to 5 V. What is the shortest pulse that can be used while ensuring full-amplitude output? For such a pulse, describe the output resulting.

For operation with 10-V output pulses with the requirement that the sum of the rise and fall times represent only 20% of the pulse width (at half amplitude), what is the slew-rate requirement for an op amp to handle pulses 2 s wide? (Note: The rise and fall times of a pulse signal are usually measured between the 10%- and 90%-height points.)

What is the highest frequency of a triangle wave of 20V peak-to-peak amplitude that can be reproduced by an op amp whose slew rate is 10 V/s? For a sine wave of the same frequency, what is the maximum amplitude of output signal that remains undistorted?

For an amplifier having a slew rate of 60 V/s, what is the highest frequency at which a 20-V peak-to-peak sine wave can be produced at the output? In designing with op amps one has to check the limitations on the voltage and frequency ranges of operation of the closed-loop amplifier, imposed by the op-amp finite bandwidth (ft), slew rate (SR), and output saturation (Vomax). This problem illustrates the point by considering the use of an op amp with ft = 2 MHz, SR = 1 V/s, and Vomax = 10 V in the design of a noninverting amplifier with a nominal gain of 10. Assume a sine-wave input with peak amplitude Vi. (a) If Vi = 0.5 V, what is the maximum frequency before the output distorts? (b) If f = 20 kHz, what is the maximum value of Vi before the output distorts? (c) If Vi = 50 mV, what is the useful frequency range of operation? (d) If f = 5 kHz, what is the useful input voltage range?