Figure P12.27 shows the CMOS version of the circuit in

A particular design of the two-stage CMOS operational amplifier of Fig. 12.1 utilizes 1-V power supplies. All transistors are operated at overdrive voltages of 0.15-V magnitude. The process technology provides devices with = 0.45 V. Find the input common-mode range and the range allowed for vO.

The CMOS op amp of Fig. 12.1 is fabricated in a process for which = 25 and = 20 . Find A1, A2,and Av if all devices are 0.5-m long and are operated at equal overdrive voltages of 0.2-V magnitude. Also, determine the op-amp output resistance obtained when the second stage is biased at 0.4 mA. What do you expect the output resistance of a unity-gain voltage amplifier to be, using this op amp?

The CMOS op amp of Fig. 12.1 is fabricated in a process for which for all devices is 24 . If all transistors have L = 0.5 m and are operated at equal overdrive voltages, find the magnitude of the overdrive voltage required to obtain a dc open-loop gain of 6400 .

This problem is identical to Problem 8.107. Consider the circuit in Fig. 12.1 with the device geometries shown at the bottom of this page. Let IREF = 225 A, for all devices = 0.75 V, nCox = 180 pCox = 60 for all devices = 9 V, VDD = VSS = 1.5 V. Determine the width of Q6, W, that will ensure that the op amp will not have a systematic offset voltage. Then, for all devices, evaluate ID, , , gm, and ro. Provide your results in a table. Also find A1, A2, the dc open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of VA on the bias currents.

Design the two-stage CMOS op amp in Fig. 12.1 to provide a CMRR of about 80 dB. If all the transistors are operated at equal overdrive voltages of 0.15 V and have equal channel lengths, find the minimum required channel length. For this technology, V/m.

A particular implementation of the CMOS amplifier of Figs. 12.1 and 12.2 provides Gm1 = 0.3 mA/V, Gm2 = 0.6 mA/V, ro2 = ro4 = 222 k, ro6 = ro7 = 111 k, and C2 = 1 pF. (a) Find the frequency of the second pole, fP2. (b) Find the value of the resistance R which when placed in series with CC causes the transmission zero to be located at s = . (c) With R in place, as in (b), find the value of CC that results in the highest possible value of ft while providing a phase margin of 80. What value of ft is realized? What is the corresponding frequency of the dominant pole? (d) To what value should CC be changed to double the value of ft? At the new value of ft, what is the phase shift introduced by the second pole? To reduce this excess phase shift to 10 and thus obtain an 80 phase margin, as before, what value should R be changed to?

A two-stage CMOS op amp similar to that in Fig. 12.1 is found to have a capacitance between the output node and ground of 0.5 pF. If it is desired to have a unitygain bandwidth ft of 150 MHz with a phase margin of 75 what must gm6 be set to? Assume that a resistance R is connected in series with the frequency-compensation capacitor CC and adjusted to place the transmission zero at infinity. What value should R have? If the first stage is operated at = 0.15 V, what is the value of slew rate obtained? If the first-stage bias current I = 100 A, what is the required value of CC?

A CMOS op amp with the topology shown in Fig. 12.1 is designed to provide mA/V and mA. (a) Find the value of that results in MHz. (b) What is the maximum value that can have while achieving a phase margin?

A CMOS op amp with the topology shown in Fig. 12.1 but with a resistance R included in series with CC is designed to provide Gm1 = 1 mA/V and Gm2 = 2 mA/V. (a) Find the value of CC that results in ft = 100 MHz. (b) For R = 500 , what is the maximum allowed value of C2 for which a phase margin of at least 60 is obtained?

A two-stage CMOS op amp resembling that in Fig. 12.1 is found to have a slew rate of 60 and a unity-gain bandwidth ft of 50 MHz. (a) Estimate the value of the overdrive voltage at which the input-stage transistors are operating. (b) If the first-stage bias current I = 100 A, what value of CC must be used? (c) For a process for which pCox = 50 A/V2, what ratio applies for Q1 and Q2?

Sketch the circuit of a two-stage CMOS amplifier having the structure of Fig. 12.1 but utilizing NMOS transistors in the input stage (i.e., Q1 and Q2).

(a) Show that the of a CMOS two-stage op amp for which all transistors have the same channel length and are operated at equal is given by (b) For , what is the minimum channel length required to obtain a of 80 dB? For the technology available, V/m.

If the circuit of Fig. 12.8 utilizes 1.65-V power supplies and the power dissipation is to be limited to 1 mW, find the values of IB and I. To avoid turning off the current mirror during slewing, select IB to be 20% larger than I.

For the folded-cascode op amp in Fig. 12.9 utilizing power supplies of 1 V, find the values of VBIAS1, VBIAS2, and VBIAS3 to maximize the allowable range of VICM and vO. Assume that all transistors are operated at equal overdrive voltages of 0.15 V. Assume for all devices is 0.45 V. Specify the maximum range of VICM and of vO.

For the folded-cascode op-amp circuit of Figs. 12.8 and 12.9 with bias currents I = 96 A and IB = 120 A, and with all transistors operated at overdrive voltages of 0.2 V, find the ratios for all devices. Assume that the technology available is characterized by = 400 and

Consider a design of the cascode op amp of Fig. 12.9 for which I = 96 A and IB = 120 A. Assume that all transistors are operated at = 0.2 V and that for all devices, = 12 V. Find Gm, Ro, and Av. Also, if the op amp is connected in the feedback configuration shown in Fig. P12.16, find the voltage gain and output resistance of the closed-loop amplifier.

Consider the folded-cascode op amp of Fig. 12.8 when loaded with a 10-pF capacitance. What should the bias current I be to obtain a slew rate of at least 10 ? If the input-stage transistors are operated at overdrive voltages of 0.2 V, what is the unity-gain bandwidth realized? If the two nondominant poles have the same frequency of 25 MHz, what is the phase margin obtained? If it is required to have a phase margin of 75, what must ft be reduced to? By what amount should CL be increased? What is the new value of SR?

Design the folded-cascode circuit of Fig. 12.9 to provide voltage gain of 80 dB and a unity-gain frequency of 10 MHz when CL = 10 pF. Design for IB = I, and operate all devices at the same . Utilize transistors with 1-m channel length for which is specified to be 20 V. Find the required overdrive voltages and bias currents. What slew rate is achieved? Also, for = 2.5 = 200 specify the required width of each of the 11 transistors used.

Sketch the circuit that is complementary to that in Fig. 12.9, that is, one that uses an input p-channel differential pair.

For the circuit in Fig. 12.11, assume that all transistors are operating at equal overdrive voltages of 0.2-V magnitude and have = 0.5 V and that VDD = VSS = 1.65 V. Find (a) the range over which the NMOS input stage operates, (b) the range over which the PMOS input stage operates, (c) the range over which both operate (the overlap range), and (d) the input common-mode range.

A particular design of the wide-swing current mirror of Fig. 12.12(b) utilizes devices having = 25, = 200 A/V2, and Vt = 0.5 V. For IREF = 100 A, what value of VBIAS is needed? Also give the voltages that you expect to appear at all nodes and specify the minimum voltage allowable at the output terminal. If VA is specified to be 10 V, what is the output resistance of the mirror?

For the folded-cascode circuit of Fig. 12.8, let the total capacitance to ground at each of the source nodes of Q3 and Q4 be denoted CP. Assuming that the incremental resistance between the drain of Q3 and ground is small, Show that the pole that arises at the interface between the first and second stages has a frequency . Now, if this is the only nondominant pole, what is the largest value that CP can be (expressed as a fraction of CL) while a phase margin of 75 is achieved? Assume that all transistors are operated at the same bias current and overdrive voltage.

In the 741 op-amp circuit of Fig. 12.13, Q1, Q2, Q5, and Q6 are biased at collector currents of 9.5 A; Q16 is biased at a collector current of 16.2 A; and Q17 is biased at a collector current of 550 A. All these devices are of the standard npn type, having IS = 1014 A, = 200, and VA = 125 V. For each of these transistors, find VBE, gm, re, r , and ro. Provide your results in table form. (Note that these parameter values are utilized in the text in the analysis of the 741 circuit.)

For the (mirror) bias circuit shown in Fig. E12.11 and the result verified in the associated exercise, find I1 for the case in which IS3 = 3 1014 A, IS4 = 6 1014 A, and IS1 = IS2 = 1014 A and for which a bias current I3 = 154 A is required.

Transistor Q13 in the circuit of Fig. 12.13 consists, in effect, of two transistors whose emitterbase junctions are connected in parallel and for which ISA = 0.25 1014 A, ISB = 0.75 1014 A, = 50, and VA = 50 V. For operation at a total emitter current of 0.73 mA, find values for the parameters VEB, gm, re, r , and ro for the A and B devices.

In the circuit of Fig. 12.13, Q1 and Q2 exhibit emitterbase breakdown at 7 V, while for Q3 and Q4 such a breakdown occurs at about 50 V. What differential input voltage would result in the breakdown of the input-stage transistors?

Figure P12.27 shows the CMOS version of the circuit in Fig. E12.11. Find the relationship between I3 and I1 in terms of k1, k2, k3, and k4 of the four transistors, assuming the threshold voltages of all devices to be equal in magnitude. Note that k denotes . In the event that k1 = k2 and k3 = k4 = 16k1, find the required value of I1 to yield a bias current in Q3 and Q4 of 1.6 mA.

For the 741 circuit, estimate the input reference current IREF in the event that 5-V supplies are used. Find a more precise value assuming that for the two BJTs involved, IS = 1014 A. What value of R5 would be necessary to reestablish the same bias current for 5-V supplies as exists for 15 V in the original design?

Design the Widlar current source of Fig. 12.14 to generate a current IC10 = 10 A given that IREF = 0.2 mA. If for the transistors, IS = 1014 A, find VBE11 and VBE10. Assume to be high.

Consider the dc analysis of the 741 input stage shown in Fig. 12.15. For what value of P do the currents in Q1 and Q2 differ from the ideal value of IC10 / 2 by 10%?

Consider the dc analysis of the 741 input stage shown in Fig. 12.15 for the situation in which IS9 = 2IS8. For IC10 = 19 A and assuming P to be high, what does I become? Redesign the Widlar source to reestablish IC1 = IC2 = 9.5 A.

For the mirror circuit shown in Fig. 12.16 with the bias and component values given in the text for the 741 circuit, what does the current in Q6 become if R2 is shorted?

It is required to redesign the circuit of Fig. 12.16 by selecting a new value for R3 so that when the base currents are not neglected, the collector currents of Q5, Q6, and Q7 all become equal, assuming that the input current IC3 = 9.4 A. Find the new value of R3 and the three currents. Recall that N = 200.

Consider the input circuit of the 741 op amp of Fig. 12.13 when the emitter current of Q8 is about 19 A. If of Q1 is 150 and that of Q2 is 200, find the input bias current IB and the input offset current IOS of the op amp.

For a particular application, consideration is being given to selecting 741 ICs for input bias and offset currents limited to 50 nA and 4 nA, respectively. Assuming other aspects of the selected units to be normal, what minimum N and what N variation are implied?

A manufacturing problem in a 741 op amp causes the current transfer ratio of the mirror circuit that loads the input stage to become 0.8 A/A. For input devices (Q1Q4) appropriately matched and with high , and normally biased at 9.5 A, what input offset voltage results?

Consider the design of the second stage of the 741. What value of R9 would be needed to reduce IC16 to 9.5 A?

Reconsider the 741 output stage as shown in Fig. 12.17, in which R10 is adjusted to make IC19 = IC18. What is the new value of R10? What values of IC14 and IC20 result?

An alternative approach to providing the voltage drop needed to bias the output transistors is the VBE multiplier circuit shown in Fig. P12.39. Design the circuit to provide a terminal voltage of 1.118 V (the same as in the 741 circuit). Base your design on half the current flowing through R1, and assume that IS = 1014 A and = 200. What is the incremental resistance between the two terminals of the VBE multiplier circuit?

For the circuit of Fig. 12.13, what is the total current required from the power supplies when the op amp is operated in the linear mode, but with no load? Hence, estimate the quiescent power dissipation in the circuit. (Hint: Use the data given in Table 12.1.)

Consider the 741 input stage as modeled in Fig. 12.18, with two additional npn diode-connected transistors, Q1a and Q2a, connected between the present npn and pnp devices, one per side. Convince yourself that each of the additional devices will be biased at the same current as Q1 to Q4that is, 9.5 A. What does Rid become? What does Gm1 become? What is the value of Ro4 now? What is the output resistance of the first stage, Ro1? What is the new opencircuit voltage gain, Gm1Ro1? Compare these values with the original ones.

What relatively simple change can be made to the mirror load of stage 1 to increase its output resistance, say by a factor of 2?

Repeat Exercise 12.15 with R1 = R2 replaced by 2-k resistors.

In Example 12.3 we investigated the effect of a mismatch between R1 and R2 on the input offset voltage of the op amp. Conversely, R1 and R2 can be deliberately mismatched (using the circuit shown in Fig. P12.44, for example) to compensate for the op-amp input offset voltage. (a) Show that an input offset voltage VOS can be compensated for (i.e., reduced to zero) by creating a relative mismatch R / R between R1 and R2, where re is the emitter resistance of each of Q1 to Q6, and R is the nominal value of R1 and R2. (Hint: Use Eq. 12.87) (b) Find R / R to trim a 5-mV offset to zero. (c) What is the maximum offset voltage that can be trimmed this way (corresponding to R2 completely shorted)?

Through a processing imperfection, the of Q4 in Fig. 12.13 is reduced to 20, while the of Q3 remains at its regular value of 50. Find the input offset voltage that this mismatch introduces. (Hint: Follow the general procedure outlined in Example 12.3.)

Consider the circuit of Fig. 12.13 modified to include resistors R in series with the emitters of each of Q8 and Q9. What does the resistance looking into the collector of Q9, Ro9, become? For what value of R does it equal Ro10? For this case, what does Ro looking to the left of node Y become?

What is the effect on the differential gain of the 741 op amp of short-circuiting one, or the other, or both, of R1 and R2 in Fig. 12.13? (Refer to Fig. 12.19.) For simplicity, assume = .

It is required to show that the loop gain of the common-mode feedback loop shown in Fig. 12.23 is approximately equal to . To determine the loop gain, connect both input terminals to ground. Break the loop at the input to the current mirror, connecting the collectors to signal ground. (This is because the original resistance between the collectors and ground is , which is small.) Apply a test current to and determine the returned current in the common collectors connection to ground, then find the loop gain as . Assume that of Q1 to Q4 is much lower than and that

An alternative approach to that presented in Example 12.4 for determining the CMRR of the 741 input stage is investigated in this problem. Rather than performing the analysis on the closed loop shown in Fig. 12.23, we observe that the negative feedback increases the resistance at node Y by the amount of negative feedback. Thus, we can break the loop at Y and connect a resistance between the common base connection of and ground. We can then determine the current i and . Using the fact that the loop gain is approximately equal to (Problem 12.48) show that this approach yields an identical result to that found in Example 12.4.

Consider a variation on the design of the 741 second stage in which R8 = 50 . What Ri2 and Gm2 correspond?

In the analysis of the 741 second stage, note that Ro2 is affected most strongly by the low value of Ro13B. Consider the effect of placing appropriate resistors in the emitters of Q12, Q13A, and Q13B on this value. What resistor in the emitter of Q13B would be required to make Ro13B equal to Ro17 and thus Ro2 half as great? What resistors in each of the other emitters would be required?

For a 741 employing 5-V supplies, and , find the output voltage limits that apply.

Consider an alternative to the present 741 output stage in which Q23 is not used, that is, in which its base and emitter are joined. Reevaluate the reflection of RL = 2 k to the collector of Q17. What does A2 become?

Consider the positive current-limiting circuit involving Q13A, Q15, and R6. Find the current in R6 at which the collector current of Q15 equals the current available from Q13A (180 A) minus the base current of Q14. (You need to perform a couple of iterations.)

Consider the 741 sinking-current limit involving R7, Q21, Q24, R11, and Q22. For what current through R7 is the current in Q22 equal to the maximum current available from the input stage (i.e., the current in Q8)? What simple change would you make to reduce this current limit to 10 mA?

Using the data provided in Eq. (12.112) (alone) for the overall gain of the 741 with a 2-k load, and realizing the significance of the factor 0.97 in relation to the load, calculate the open-circuit voltage gain, the output resistance, and the gain with a load of 200 .

A 741 op amp has a phase margin of 75. If the excess phase shift is due to a second single pole, what is the frequency of this pole?

A 741 op amp has a phase margin of 75. If the op amp has nearly coincident second and third poles, what is their frequency?

For a modified 741 whose second pole is at 5 MHz, what dominant-pole frequency is required for 80 phase margin with a closed-loop gain of 100? Assuming CC continues to control the dominant pole, what value of CC would be required?

An internally compensated op amp having an ft of 10 MHz and dc gain of 106 utilizes Miller compensation around an inverting amplifier stage with a gain of 1000. If space exists for at most a 50-pF capacitor, what resistance level must be reached at the input of the Miller amplifier for compensation to be possible?

Consider the integrator op-amp model shown in Fig. 12.33. For Gm1 = 5 mA/V, CC = 100 pF, and a resistance of shunting CC, sketch and label a Bode plot for the magnitude of the open-loop gain. If Gm1 is related to the first-stage bias current as Gm1 = I/2VT, find the slew rate of this op amp.

For an amplifier with a slew rate of 10 V/s, what is the full-power bandwidth for outputs of 10 V? What unity-gain bandwidth, t, would you expect if the topology was similar to that of the 741?

Figure P12.63 shows a circuit suitable for opamp applications. For all transistors = 100, VBE = 0.7 V, and ro = . (a) For inputs grounded and output held at 0 V (by negative feedback) find the collector currents of all transistors. Neglect base currents. (b) Calculate the input resistance. (c) Calculate the gain of the amplifier with a load of 5 k. (d) With load as in (c) calculate the value of the capacitor C required for a 3-dB frequency of 100 Hz.

Design the circuit in Fig. 12.38 to generate a current I = 6 A. Utilize transistors and having areas in a ratio of 1:4. Assume that and are matched and design for a 0.2-V drop across each of and Specify the values of and Ignore base currents.

Consider the circuit of Fig. 12.38 for the case designed in Exercise 12.28, namely, I = 10 A, , , . Augment the circuit with npn transistors and with emitters connected to ground and bases connected to , to generate constant currents of 10 A and 40 A, respectively. What should the emitter areas of and be relative to that of ? What value of a resistance will, when connected in the emitter of , reduce the current generated by to 10 A? Assuming that the line has a low incremental resistance to ground, find the output resistance of current source and of current source with connected. Ignore base currents.

(a) Find the input common-mode range of the circuit in Fig. 12.40(a). Let V and 2.3 V. (b) Give the complementary version of the circuit in Fig. 12.40(a), that is, the one in which the differential pair is npn. For the same conditions as in (a), what is the input commonmode range?

For the circuit in Fig. 12.40(b), let V, V, I = 20 A, and . Find the input common-mode range and the differential voltage gain . Neglect base currents.

For the circuit in Fig. 12.41, let V, V, and A. Find that results in a differential gain of 10 V/V. What is the input commonmode range and the input differential resistance? Ignore base currents except when calculating

It is required to find the input resistance and the voltage gain of the input stage shown in Fig. 12.42. Let V so that the pair is off. Assume that supplies 6 A, that each of to is biased at 6 A, and that all four cascode transistors are operating in the active mode. The input resistance of the second stage of the op amp is 1.3 M . The emitter degeneration resistances are k , and k . [Hint: Refer to Fig. 12.43.]

Consider the equivalent half-circuit shown in Fig. 12.43. Assume that in the original circuit, is biased at a current I, and are biased at 2I, the dc voltage drop across is 0.2 V, and the dc voltage drop across is 0.3 V. Find the open-circuit voltage gain (i.e., the voltage gain for ). Also find the output resistance in terms of I. Now with connected, find the voltage gain in terms of . For , find I that will result in the voltage gains of 160 V/V and 320 V/V.

(a) For the circuit in Fig. 12.44, show that the loop gain of the common-mode feedback loop is Recall that the CMF circuit realizes the transfer characteristic . Ignore the loading effect of the CMF circuit on the collectors of the cascode transistors. (b) For the values in Example 12.6, calculate the loop gain . (c) In Example 12.6, we found that with the CMF absent, a current mismatch A gives rise to V. Now, with the CMF present, use the value of loop gain found in (b) to calculate the expected and compare to the value found by a different approach in Example 12.6. [Hint: Recall that negative feedback reduces change by a factor equal to

The output stage in Fig. 12.46 operates at a quiescent current of 0.4 mA. The maximum current that the stage can provide in either direction is 10 mA. Also, the output stage is equipped with a feedback circuit that maintains a minimum current of in the inactive output transistor. (a) What is the allowable range of (b) For , what is the output resistance of the op amp? (c) If the open-loop gain of the op amp is 100,000 V/V, find the closed-loop output resistance obtained when the op amp is connected in the unity-gain voltage follower configuration, with (d) If the op amp is sourcing a load current find and the open-loop output resistance. (e) Repeat (d) for the case of the open-loop op amp sinking a load current of 10 mA.

It is required to derive the expressions in Eqs. (12.132) and (12.133). Toward that end, first find in terms of and hence Then find in terms of For the latter purpose note that measures and develops a current . This current is supplied to the series connection of and where In the expression you obtain for use the relationship to express in terms of and Now with and determined, find and

It is required to derive the expression for in Eq. (12.134). Toward that end, note from the circuit in Fig. 12.48 that and note that conducts a current and conducts a current given by Eq. (12.133).

For the output stage in Fig. 12.48, find the current that results in a quiescent current Assume that I = 10 A, has eight times the area of , and has four times the area of . What is the minimum current in